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Browse Prior Art Database

Prefetching With Invalid Cache Entries

IP.com Disclosure Number: IPCOM000101540D
Original Publication Date: 1990-Aug-01
Included in the Prior Art Database: 2005-Mar-16
Document File: 1 page(s) / 38K

Publishing Venue

IBM

Related People

Liu, L: AUTHOR

Abstract

In the preceding article the observation was made that decisions upon a cache miss fetch may utilize information at invalidated cache directory entries to optimize MP cache design with EX states. In this article we deal with prefetching of cache lines with similar information.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 83% of the total text.

Prefetching With Invalid Cache Entries

       In the preceding article the observation was made that
decisions upon a cache miss fetch may utilize information at
invalidated cache directory entries to optimize MP cache design with
EX states.  In this article we deal with prefetching of cache lines
with similar information.

      One problem in future multiprocessor (MP) systems is the
XI-invalidation impact on cache hit ratios.  That is, even when
caches get bigger due to technology advances, the hit ratio growth
will be limited due to XI-invalidations on shared data lines.  One
approach to remedying this problem is to prefetch lines that were
previously XI-invalidated.

      As in the preceding article, when a cache directory entry is
XI-invalidated (e.g., due to remote processor store) the entry is
marked invalid in a special way such that the line address
information is still recognizable. Now, upon a cache miss, the cache
control looks up the directory and sees whether there are surrounding
lines with such special invalid status.  If so, prefetching of some
or all of these lines will be carried out, in addition to the miss
fetch of currently the accessed line.

      Related Issues
(a)  The range of surrounding lines may be determined with various
criteria.  For instance, they could be searched in the range of
surrounding 4 lines (e.g., in a storage block of 4 line partitioning
by address bits, or 1 preceding and 2 following).
(b)  It is also p...