Browse Prior Art Database

Asynchronous State Machine Using Programmable Logic

IP.com Disclosure Number: IPCOM000101542D
Original Publication Date: 1990-Aug-01
Included in the Prior Art Database: 2005-Mar-16
Document File: 2 page(s) / 67K

Publishing Venue

IBM

Related People

Nathanson, BJ: AUTHOR

Abstract

Disclosed is a structure technique for building edge-triggered state machines with a commercial programmable-logic device. One application would be interfacing to an asynchronous bus such as the MICRO CHANNEL*.

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This is the abbreviated version, containing approximately 52% of the total text.

Asynchronous State Machine Using Programmable Logic

       Disclosed is a structure technique for building
edge-triggered state machines with a commercial programmable-logic
device.  One application would be interfacing to an asynchronous bus
such as the MICRO CHANNEL*.

      The programmable-logic chip is the Lattice GAL 6001. Each of
this chip's output registers can be clocked with a Boolean
sum-of-product expression.  This ability is key to implementation.
Most other chips restrict the register clocks to be product terms.

      Each state and output register is connected as shown in the
figure.  The data input is connected to the flip-flop's inverting
output -- that is, the register is connected as a T flip-flop that
will change state every time it is clocked. The clock input is
connected to a 2:1 multiplexer (MUX). This multiplexer is, of course,
implemented with the part's programmable logic.

      The mux's 0 input is activated by the logical conditions that
will drive the flip-flop active; the 1 input is activated by the
logical conditions that will drive it inactive.  The mux select input
is connected to the output of the flip-flop, so that when the
flip-flop is inactive, the mux selects input 0, and when it is
active, it selects input 1.

      Output signals and state registers both use this technique.  In
both cases, the mux inputs are a function of state machine inputs and
the state machine's current state.

      The flip-flop is made initially inactive.  The mux ensures that
the flip-flop can be clocked only by the conditions that will make it
go a...