Browse Prior Art Database

Multiple Releases of EX Status in MP Caches

IP.com Disclosure Number: IPCOM000101544D
Original Publication Date: 1990-Aug-01
Included in the Prior Art Database: 2005-Mar-16
Document File: 2 page(s) / 112K

Publishing Venue

IBM

Related People

Liu, L: AUTHOR

Abstract

Disclosed is a method for reducing cross-interrogate (XI) activities in multiprocessor (MP) caches using EX (exclusive) states. It is typical for an MP cache design to record in cache directories for individual lines entries. From performance analysis it was identified that XI activities tend to cluster around lines close to each other in memory. The basic idea of this invention is to manipulate EX status for multiple lines in one XI event in order to reduce the probability of subsequent XIs. The discussions will be presented mainly for store-thru MP cache designs.

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Multiple Releases of EX Status in MP Caches

       Disclosed is a method for reducing cross-interrogate (XI)
activities in multiprocessor (MP) caches using EX (exclusive) states.
It is typical for an MP cache design to record in cache directories
for individual lines entries. From performance analysis it was
identified that XI activities tend to cluster around lines close to
each other in memory.  The basic idea of this invention is to
manipulate EX status for multiple lines in one XI event in order to
reduce the probability of subsequent XIs.  The discussions will be
presented mainly for store-thru MP cache designs.

      Consider an MP design with N processors, each has a store-thru
private cache.  Each cache directory entry records the status of the
line as either INV (invalid), RO (read-only) or EX (exclusive).  Each
time a line in a cache acquires EX status (e.g., for a processor
store) all copies of the line in remote caches are invalidated
properly.

      EX status allows processors to store into a cache line without
delays of synchronizing with other processors. However, when EX
status is used in MP design, we have the problem of
Cross-Interrogates (XIs).  An XI means the situation in which one
processor accesses a line that is EX at a remote processor cache.
Normally the resolution of XI condition involves the communications
with remote processor for release of EX status and is costly in
performance.  One approach to reduce the XI penalties is to allow
remote caches to release EX status of those lines that tend to be
XIed in the near future.

      Now considered is the storage logically partitioned into
blocks.  Each block consists of a multiplicity (e.g., 8) of
contiguous lines.  For a given line L the associated block is denoted
as BL .  Consider the XI situation when a processor P accesses a line
L that is held EX by a remote processor P'.  The key operation of the
invention is upon such XI situation as follows.  The processor P' is
cross-interrogated to release its EX status on L.  (If P is
requesting EX status on L as well the copy at P' should also be
invalidated.)  The cache control at P' will release the possible EX
status of all the lines (including L) of the block BL in its cache
directory.  The new status of each of such a line released of EX
status becomes RO or INV (invalidate will occur when P actually needs
the particular line(s) with EX status).  P' may signal completion of
this particular XI operation (e.g., to P directly, or through a
centralized storage control) as soon as the status change for the
line(s) being demanded by P has been in effect.  The status changes
for the rest of lines (of BL) may be done at P' in later cycle(s).

      With proper implementation it is not necessary for the XI
target processor (P' in the example above) to separately signal the
changes of status (e.g., to central storage control) on individual
lines (in BL).  However, i...