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C-Segment Handling With Randomization of DLAT Entry Selection With STOs

IP.com Disclosure Number: IPCOM000101549D
Original Publication Date: 1990-Aug-01
Included in the Prior Art Database: 2005-Mar-16
Document File: 2 page(s) / 94K

Publishing Venue

IBM

Related People

Kienzle, MG: AUTHOR [+2]

Abstract

In System/370 architecture C-Segments (Common Segments) are defined such that DLAT address translation will benefit by sharing such page entries among different address spaces (STOs). However, conventional implementations will cause difficulties in randomizing DLAT congruence class selection via STO (ID/Address) bits. We observe that, according to the architecture definition, the STOs of C-Segment pages are practically useless in DLAT. For C-Segment pages, the DLAT implementation may simply index to DLAT congruence classes differently. Then DLAT congruence class randomization with STO bits will not cause C-Segment entries to be duplicated in DLAT. However, one problem we have to solve is to efficiently detect whether or not a virtual page is in a C-Segment, so that the congruence class selection may be kicked off early.

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C-Segment Handling With Randomization of DLAT Entry Selection With STOs

       In System/370 architecture C-Segments (Common Segments)
are defined such that DLAT address translation will benefit by
sharing such page entries among different address spaces (STOs).
However, conventional implementations will cause difficulties in
randomizing DLAT congruence class selection via STO (ID/Address)
bits.  We observe that, according to the architecture definition, the
STOs of C-Segment pages are practically useless in DLAT.  For
C-Segment pages, the DLAT implementation may simply index to DLAT
congruence classes differently.  Then DLAT congruence class
randomization with STO bits will not cause C-Segment entries to be
duplicated in DLAT.  However, one problem we have to solve is to
efficiently detect whether or not a virtual page is in a C-Segment,
so that the congruence class selection may be kicked off early.

      Let us pick a particular STO (e.g., all 0-bits), which will be
denoted as STO0 .  We consider a bit-vector, called C-vector, of
length 2K.  For a given virtual address A, we use address bits 1-11
(which gives the STX in 370 architecture) to index to the C-vector to
determine whether the segment is C-segment or not.  The indexed bit
is denoted as C(A).  There are two possibilities:
o    When C(A) is ON, A is in a C-segment.  In this case STO0 is
used as the STO.
o    Otherwise A is assumed as not in C-segment.  The regular STO (in
Control Register 1) is assumed.

      The C-vector is null (all O-bits) at the beginning. When a DLAT
miss occurs, and when the translation process finds the page in
C-segment, the associated C[A] bit is turned ON, and the new
translation information is put into DLAT assuming STO0 as the STO
(the page entry should not be in DLAT at the moment, if C-bits are
interpreted by all address spaces).  However, if the translation
finds the page not in C-segment, no operation is required on
C-vector, and the translation information for the page is put into
DLAT assuming regular STO.  In doing so, it may happen that a page
address in a C-segment finds the bit in C-vector OFF, since it was
not yet turned ON (this should be statistically ignorable).  However,
whenever the C[A] bit is ON, it is guaranteed that the page is in
C-segment.  Bits in the C-vector should be turned OFF at proper
times.  For instance, when a C-segment is purged (or...