Browse Prior Art Database

Method for high-speed wire-bonded interconnects

IP.com Disclosure Number: IPCOM000101571D
Publication Date: 2005-Mar-16
Document File: 2 page(s) / 32K

Publishing Venue

The IP.com Prior Art Database

Abstract

Disclosed is a method for high-speed wire-bonded interconnects. Benefits include improved functionality, improved performance, and improved cost effectiveness.

This text was extracted from a Microsoft Word document.
This is the abbreviated version, containing approximately 55% of the total text.

Method for high-speed wire-bonded interconnects

Disclosed is a method for high-speed wire-bonded interconnects. Benefits include improved functionality, improved performance, and improved cost effectiveness.

Background

              In conventional wire bonding, a single wire bond from each functional pad of the silicon is connected to the package interconnect substrate. For example, a 2-mm to 3-mm long wire with a 25-µm diameter results in ~175-mOhms resistance. Doubling the wire diameter to 50 µm reduces the resistance by 4X to ~44 mOhms. However, a larger nonstandard bonding pad, a larger passivation opening of ~91 µm, and a larger silicon surface area are required.

General description

              The disclosed method connects two wires instead of a single wire between the silicon pad and the interconnect package substrate. The two wires are configured in an unparallel noncontiguous shape to minimize mutual inductive coupling. This double connection improves the electrical performance and bandwidth of the wire-bond interconnection. The method extends the technology boundary to higher frequency applications.

              The disclosed method applies to high-speed devices that operate in the 1-10 GHz range, such as RF and wireless components. The method supports low package costs and small form factors. Additionally, the disclosed method may benefit double data rate and packetized interfaces.

Advantages

              The disclosed method provides advantages, including:
•             Improved functionality due to connecting two wires between the silicon pad and the interconnect package substrate
•             Improved performa...