Browse Prior Art Database

Method for an antipad void

IP.com Disclosure Number: IPCOM000101578D
Publication Date: 2005-Mar-16
Document File: 4 page(s) / 136K

Publishing Venue

The IP.com Prior Art Database

Abstract

Disclosed is a method for an antipad void. Benefits include improved functionality, improved reliability, and improved yield.

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Method for an antipad void

Disclosed is a method for an antipad void. Benefits include improved functionality, improved reliability, and improved yield.

Background

      Suppliers experience high yield loss in flip-chip ball grid array (FCBGA) package designs due to foreign material (FM) fallout.

      Conventional antipads have a round (oval) shape. Trace spacing is uniform at 32 µm. potentially subjected to DFR lifting issue during photolithographic development and copper plating in substrate SAP processing, causing FM and leakages in e-testing and highly accelerated stress test (HAST) reliability testing (see Figure 1).

      The plane-to-land spacing has decreased from 50 µm to 36 µm, weakening the dry film resist (DFR) adhesion strength. This trend may indicate increased yield loss as spacing reduces to 32 µm (see Figures 2 and 3).

      The top 3.84% electrical-test (e-test) leakage failures are caused by copper residue (see Figure 4).

      Antipad designs are automated by an advance package design (APD) computer aided design (CAD) tool.

              The conventional method of increasing DFR adhesion strength is to increase the metal plane-to-pad spacing. However, this approach decreases the electrical performance for signal referencing in term of insertion loss and return loss (see Figure 5).

General description

      The disclosed method uses an antipad voiding design to prevent dry film resist lamination in semiadditive process (SAP) copper plating process.

Advantages

              The disclosed method provides advantages, including:
•             Improved functionality due t...