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Modified Electroplated Metal with an Inert Particles Matrix to Control Stress in Vias or Trenches

IP.com Disclosure Number: IPCOM000101590D
Publication Date: 2005-Mar-16
Document File: 2 page(s) / 64K

Publishing Venue

The IP.com Prior Art Database

Abstract

Disclosed is a method that controls the thermal stress in the silicon substrates by depositing a plated metal (e.g. copper) and inert particles in the matrix layer in vias or trenches.

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Modified Electroplated Metal with an Inert Particles Matrix to Control Stress in Vias or Trenches

Disclosed is a method that controls the thermal stress in the silicon substrates by depositing a plated metal (e.g. copper) and inert particles in the matrix layer in vias or trenches.

Background

Currently, thermal stress cracks in silicon substrates form as a result of filling vias or trenches with plated metal. Differences in the coefficient of thermal expansion (CTE) cause stress cracks. Interconnects are manufactured by etching vias or trenches in the silicon substrate. A barrier seed is deposited in the vias or trenches, and then they are filled with copper in the plating process (see Figure 1). However, in this process the dual damascene process copper expands and exerts thermal stress on the silicon material when a current is applied to it.

Another way to reduce the thermal stress is to move the point of pressure and electrical contact (i.e. C4 bump) away from the vias by a trace. However, the drawback to this approach is that additional resistance is introduced by the trace and offset bump, and real estate is further limited on the wafer.

General Description

In the disclosed method, after forming a via or trench using established processes, a thin layer of inert particles in a metallic copper matrix (preferably a Teflon-copper) is plated to a thickness between 0.5 and 1 micron (see Figure 2). This is followed by a standard copper plating process designed to fill the via...