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CPU Substrate Spacer for an Integrated Heat Spreader on a Multi-Die Electronic Package

IP.com Disclosure Number: IPCOM000101591D
Publication Date: 2005-Mar-16
Document File: 3 page(s) / 59K

Publishing Venue

The IP.com Prior Art Database

Abstract

Disclosed is a method for a spacer used between the Integrated Heat Spreader (IHS) and the CPU substrate for multi-die electronic packages. Benefits include improving the bond line for the Thermal Interface Material (TIM) and improving the load distribution from the IHS to the package.

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CPU Substrate Spacer for an Integrated Heat Spreader on a Multi-Die Electronic Package

Disclosed is a method for a spacer used between the Integrated Heat Spreader (IHS) and the CPU substrate for multi-die electronic packages. Benefits include improving the bond line for the Thermal Interface Material (TIM) and improving the load distribution from the IHS to the package.

Background

Currently, load distributions from the IHS to the package and adequate bond line TIM thicknesses are concerns with multi-die electronic packages. This is particularly true for high compressive retention loads, or for low stiffness (i.e. thin or coreless) electronic packages.

Figure 1 shows the cross section of a typical multi-die package using an IHS. In a typical microprocessor application, a sustained compressive load is applied on top of the IHS; for a Land Grid Array (LGA) socket case, this compressive load may be substantial (i.e. >100lbs). Figure 2 shows the cross section of a typical configuration of a LGA solution. The retention solution applies a sustained compressive load on top of the IHS to create an electrical connection between the package and an LGA socket. 

Figure 3 shows the package and IHS deforming to the point where the IHS post mechanically couples to the package, transferring the load from the IHS into the package.   

General Description

Figure 4 shows the cross section of a multi-die package using an IHS with the disclosed method’s spacer positioned between two die. Sp...