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Method for a carbon-nanotube IHS

IP.com Disclosure Number: IPCOM000101593D
Publication Date: 2005-Mar-16
Document File: 5 page(s) / 74K

Publishing Venue

The IP.com Prior Art Database

Abstract

Disclosed is a method for a carbon nanotubes integrated heatsink (IHS). Benefits include improved functionality, improved thermal performance, and improved performance.

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Method for a carbon-nanotube IHS

Disclosed is a method for a carbon nanotubes integrated heatsink (IHS). Benefits include improved functionality, improved thermal performance, and improved performance.

Background

              A major impediment to the future performance of microprocessors is the requirement to remove heat from circuits, particularly at hot spots. The conventional copper IHS must be replaced with a thinner, high thermal conductivity material.

              A point of resistance to the transfer of heat from the device layer to the heat spreader is the thermal interface material (TIM) between the die and the IHS. TIM is a material with low thermal conductivity, such as indium.

              Conventional cooling solutions have a thin layer of an adhesive material between the silicon die and a heat spreader/heatsink. TIM material is sandwiched between the die and the IHS. This layer is designated as TIM 1. Another TIM layer is sandwiched between the IHS and the heatsink. This layer is designated as TIM 2. The capability to reduce qjc and the CTE mismatch between the die and IHS is important for package performance and reliability (see Figure 1).

General description

              The disclosed method is a high-thermal-conductivity integrated heatsink (IHS) using carbon nanotubes (CNTs) to enhance thermal conductivity of the heat spreader. The hybrid IHS can be used as a standalone heat spreader. The IHS can be used in a thin-die thin-TIM (TDTT) configuration. Additionally, the IHS can be used in a vertical stacking of multiple die in a three-dimensional configuration. The IHS facilitates vertical stacking due to its small form factor and thinness. A silicon die can be attached to the hybrid IHS by a direct wafer-bonding process, eliminating the requirement for TIM. The polished surface of the backside of the die directly contacts the polished surface of the hybrid die. The bonding can occur at room temperature but must be followed by a heat treatment at temperatures below ~ 400°C.

      The key elements of the method include:

•             Etching trenches 10 to 40 microns deep that are appropriately spaced apart in a silicon wafer

•             Deposition of Co or Ni catalyst in the trenches

•             Use of plasma-enhanced chemical vapor deposition (PECVD) processes to grow aligned CNTs in the trenches in the silicon wafer

•             Use of sputtering to deposit material, such as silicon, copper or titanium, to encapsulate the CNTs

•             Thin and polish the substrate silicon to the required final thickness

•             Direct bonding the die to the silicon IHS and heating to temperatures ~ 250°C to complete the bonding process

Advantages

              The disclosed method provides advantages, including:

•             Improved functionality due to providing a high-thermal-conductivity IHS without the use of TIM

•             Improved functionality due to providing a thin, small form factor IHS for improved vertical stacking

•         ...