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Browse Prior Art Database

Maskable Transition Latch for Delay Testing

IP.com Disclosure Number: IPCOM000101607D
Original Publication Date: 1990-Aug-01
Included in the Prior Art Database: 2005-Mar-16
Document File: 2 page(s) / 66K

Publishing Venue

IBM

Related People

Vincent, BJ: AUTHOR

Abstract

AC testing of all internal latch nodes becomes possible by including appropriate clocks, adding some latch circuit area, and employing an appropriate test algorithm. The method provides storage of a transition state at latches, thus permitting AC test coverage approximating coverage by DC testing. Additionally, speed or performance sorting and detection of timing problems are made possible.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 52% of the total text.

Maskable Transition Latch for Delay Testing

       AC testing of all internal latch nodes becomes possible
by including appropriate clocks, adding some latch circuit area, and
employing an appropriate test algorithm.  The method provides storage
of a transition state at latches, thus permitting AC test coverage
approximating coverage by DC testing.  Additionally, speed or
performance sorting and detection of timing problems are made
possible.

      Referring to the figure, latch L3 is added to standard double
latch L1 to form a stable shift register latch (SSRL).  Feedback from
latch L3 is connected to input M of AND gate 2.  Transition clock T
is connected to the other AND 2 input.  Output from AND 2 goes to
load transit clock input LT of latch L1.  Latch L3 holds mask data
that ultimately determines whether or not a transition occurs on
output from system latch L2 when clock B pulses.  A "1" in latch L3
means that a transition is desired on the latch L2 output and a "0"
in latch L3 indicates that latch L2 output should remain unchanged.

      A transition clock input T to AND 2 when latch L3 contains a
"1" loads latch L2 inverted output 4 into X of latch L1.  B clock
input to L2 transfers X data in L1 to latch L2, resulting in a 0->1
or 1->0 transition on L2 output.

      If latch L3 contains a "0", a T clock input has no effect on
contents of latch L1.  B clock input then does not change L2 output,
thus producing a 0->0 or 1->1 on L2 output.

      A full description of maskable transition latch signals
follows:
A - scan clock that latches scan data into latch L...