Browse Prior Art Database

Submicron CMOS Gate Array

IP.com Disclosure Number: IPCOM000101611D
Original Publication Date: 1990-Aug-01
Included in the Prior Art Database: 2005-Mar-16
Document File: 3 page(s) / 164K

Publishing Venue

IBM

Related People

Chen, CL: AUTHOR

Abstract

A technique is described whereby logic circuitry is structured in submicron proportions so as to provide variable size circuit wiring density and improve performance of a gate array. Discussed are submicron array structures for on-chip master/slave latches, registers, a dual- purpose memory/logic array, meshed power/ground distribution and other features in the gate array.

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This is the abbreviated version, containing approximately 37% of the total text.

Submicron CMOS Gate Array

       A technique is described whereby logic circuitry is
structured in submicron proportions so as to provide variable size
circuit wiring density and improve performance of a gate array.
Discussed are submicron array structures for on-chip master/slave
latches, registers, a dual- purpose memory/logic array, meshed
power/ground distribution and other features in the gate array.

      Typically, logic circuit implementation using gate array, also
called masterslice, can achieve fast fabrication turn-around as
compared to other design approaches, such as semi-custom masterimage
design or hand-horn custom design. However, the trade-off of using
such gate array designs is its poor circuit density and speed
characteristics relative to other techniques.

      Generally, a gate array is assembled by means of a large
portion of transistor image, with fixed wiring channels between them,
and a static random-access memory (SRAM).  The size of the SRAM
depends on the intended application.  Once an area is dedicated to a
SRAM, it cannot be used for other purposes.  It has always been a
problem for a masterslice to have a floor-plan which can provide both
a large number of logic circuits and a proper size of SRAM.  Some
novel approaches, such as the Sea of Gates array and configurable
SRAM/logic cells embedded inside a logic array, have been proposed.
The Sea of Gates approach may increase logic circuit counts but still
not be able to provide the proper size of SRAM.  The configurable
approach suffers from performance degradation by spreading out its
SRAM cells.

      The concept described herein provides several methods of
constructing a submicron gate array using polycide wiring with
enhanced on-chip LSSD registers, dual-purpose memory/logic image and
power busing configurations.

      ARRAY STRUCTURED BY ON-CHIP LSSD REGISTERS Depending on the
circuit chip size, the chip is divided into columns.  Within each
column it is further sectioned into small logic images by means of
on-chip master/slave (M/S) latches, also called L1/L2 scan latches,
or LSSD registers.  The LSSD registers are essential in achieving a
race-free logic implementation and to provide testability in most
logic chips.

      Since more and more LSSD registers are generally needed to
implement highly integrated complex logic chips, a LSSD register is
typically used as the storage element to set up both the input and
output for large logic macros.  A LSSD register has a regular
structure similar to a SRAM cell.  However, it is inefficient when
trying to build such a register in a gate array image. Typically, the
wide wiring-channel in a gate array cannot be completely used for
implementing a repeated and localized logic function.  The
pre-fabricated on-chip LSSD registers can achieve a custom design
circuit density when they are actually used for supplying logic
inputs and outputs. However, when it is not used, the area o...