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Multiple-Valued Logic Storage Elements

IP.com Disclosure Number: IPCOM000101613D
Original Publication Date: 1990-Aug-01
Included in the Prior Art Database: 2005-Mar-16
Document File: 2 page(s) / 73K

IBM

Related People

Barcelo, P: AUTHOR [+3]

Abstract

This article describes circuits for latching multiple-valued logic (MVL) values by a D latch, an edge-triggered multi-flop, and a maximum-valued latch.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 52% of the total text.

Multiple-Valued Logic Storage Elements

multiple-valued logic (MVL) values by a D latch, an edge-triggered
multi-flop, and a maximum-valued latch.

There is an increasing interest in the use of MVL systems.  A
MVL system is a logic system with a radix greater than 2.  Binary has
been the dominant system over the past few decades, but integrated
circuit densities have reached a point where MVL systems are
feasible.  In order to implement sequential MVL systems, the basic
building blocks are needed.  The basic MVL operators (OR, AND,
INVERT, and CYCLE) have been defined by MVL algebra, also known as
Postian algebra.  These operators can be implemented as logic gates
which, in turn, can be used to create the basic building blocks, such
as the MVL storage elements presented herein.  The MVL storage
elements, unlike their binary counterparts, can store one of several
states.  The following MVL functions are used to design the MVL
storage elements:
1.   A  AND  B  =  Minimum of A,B
2.   A  OR   B  =  Maximum of A,B
The actual electronic implementation of these gates depends on the
radix of the MVL system desired.

Figs. 1-4 illustrate circuits that will function with any
radix.  The MVL D latch is illustrated in Fig. 1.  The clock signal
for the MVL D latch is shown in Fig. 2.  This signal toggles from its
inactive logical state of zero, to its active logical state of N-1;
where N = radix.  For example, where the radix is equal to four, t...