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Discriminative Stress for FET Circuits by Ion Implantation

IP.com Disclosure Number: IPCOM000101621D
Original Publication Date: 1990-Aug-01
Included in the Prior Art Database: 2005-Mar-16
Document File: 1 page(s) / 31K

Publishing Venue

IBM

Related People

Euen, W: AUTHOR [+2]

Abstract

Ordinary functional tests frequently fail in immediately detecting gate oxide defects of FET devices. However, after a certain number of switch operations, such defects lead to device failure. This article describes a method of selectively and simultaneously marking defective gate oxides such that they are immediately detected in their entirety by the first ordinary functional tests.

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Discriminative Stress for FET Circuits by Ion Implantation

       Ordinary functional tests frequently fail in immediately
detecting gate oxide defects of FET devices.  However, after a
certain number of switch operations, such defects lead to device
failure.  This article describes a method of selectively and
simultaneously marking defective gate oxides such that they are
immediately detected in their entirety by the first ordinary
functional tests.

      The method consists in using ion implantation to simultaneously
subject all gates to an electrical stress. The gate capacitors are
charged by the ion stream to their breakdown voltage.  Provided the
discharge current density has been properly adjusted by the ion
current of the implanter, only defective gates are destroyed.  It may
be favorable to increase the temperature during implantation, which
is achieved by a heated substrate (wafer) holder.

      Implantation energy and ion type are not of primary importance
but may be selected according to a given device structure.  Depending
on the respective device, stress and doping implantation may be
identical.

      Using standard equipment, the proposed method permits
subjecting all gates on the wafer to rapid and contactless stress,
thus reducing the early fail rate.