Browse Prior Art Database

Memory Strip Module

IP.com Disclosure Number: IPCOM000101627D
Original Publication Date: 1990-Aug-01
Included in the Prior Art Database: 2005-Mar-16
Document File: 1 page(s) / 36K

Publishing Venue

IBM

Related People

Klink, E: AUTHOR [+2]

Abstract

Single in-line memory modules (SIMMs) are usually manufactured in several standard process steps. After the various chips have been processed and tested, the wafers are diced, the good and partially good chips are selected and finally packaged into standard housings, such as SOJs (small outline J-leads).

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This is the abbreviated version, containing approximately 92% of the total text.

Memory Strip Module

       Single in-line memory modules (SIMMs) are usually
manufactured in several standard process steps.  After the various
chips have been processed and tested, the wafers are diced, the good
and partially good chips are selected and finally packaged into
standard housings, such as SOJs (small outline J-leads).

      The above-mentioned steps show that two packaging levels are
required for building SIMMs.  The approach described below eliminates
one packaging level and several process steps.

      The area between the chips, which is generally used for test
structures (KERF), is also occupied by bus and power wiring
comprising DATA, RAS, CAS, ADDR, WRITE lines, etc. This common bus is
supplied with pads at periodic intervals, which are employed for
testing and final connection.  With the third metallization, all pads
are connected to the common bus, so that all chips contact the bus.
After wafer testing, the memory strip is configured by (say, laser)
detaching defective chips from the common bus.  Partially good chips
remain connected to the memory strip.  The configuration is finalized
by dicing the strips and mounting on the SIMM card by C4 or bonding.
The strip glued to the SIMM card is finally protected by coating.

      The proposed solution significantly reduces the packaging
process and the costs involved.  It offers increased flexibility in
the use of partially good chips. In addition, the SIMM real estate is
decreased...