Browse Prior Art Database

Compact Dummy Word Line for Sense System Timing Chain

IP.com Disclosure Number: IPCOM000101631D
Original Publication Date: 1990-Aug-01
Included in the Prior Art Database: 2005-Mar-16
Document File: 3 page(s) / 81K

Publishing Venue

IBM

Related People

Clemen, R: AUTHOR [+2]

Abstract

A compact dummy word line scheme is proposed which, compared with a regular static 6-D memory cell, requires only two instead of six NFETs for the dummy cell.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 52% of the total text.

Compact Dummy Word Line for Sense System Timing Chain

       A compact dummy word line scheme is proposed which,
compared with a regular static 6-D memory cell, requires only two
instead of six NFETs for the dummy cell.

      A dummy word line is extracted from the 6-D memory cell by
eliminating the four flip-flop devices.  Only the word line and the
two associated I/O devices are retained, as they provide the load and
determine the rise time of the word line signal (Fig. 1B).  To obtain
the same gate capacitances as for the memory cell, one device has its
drain and source tied to VDD, whereas the other is connected to
ground.  This connection corresponds to the steady state of the real
memory cell, where one storage node is charged to VDD, while the
other is at ground.  (As a second-order effect, the device gate
capacitance depends on the gate/source and the gate/drain voltages.)

      The layout of the NFET device and the word line is the same for
the regular cell.  Thus, the total capacitance of the dummy word line
is the same as for a word line within the array.  The dummy word
decoder DWD is placed in the timing chain channel, using the same
circuit and layout as for the ordinary decoder.

      Referring to the block and the timing diagrams of Figs. 1A to
1C, the timing scheme operates as follows.

      Initiated by the (external) chip select clock CS, the timing
chain generates the various clock phases controlling the data
transfer in the storage array.  First, a regular word decoder WD as
well as the dummy word decoder DWD are activated simultaneously in
parallel circuit paths by the respective front-end driver SWDDR.
Thus, the dummy word line DWL of the timing chain is driven up at the
same time...