Browse Prior Art Database

Dual-Address Decoding Scheme

IP.com Disclosure Number: IPCOM000101636D
Original Publication Date: 1990-Aug-01
Included in the Prior Art Database: 2005-Mar-16
Document File: 2 page(s) / 61K

Publishing Venue

IBM

Related People

Loehlein, WD: AUTHOR [+2]

Abstract

Every time a processor performs a storage access operation, the first step is to calculate the storage address. The next step may be parallel address translation by a TLB (table look-aside buffer) and accessing a cache and its cache directory.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 63% of the total text.

Dual-Address Decoding Scheme

       Every time a processor performs a storage access
operation, the first step is to calculate the storage address.  The
next step may be parallel address translation by a TLB (table
look-aside buffer) and accessing a cache and its cache directory.

      Calculation of the storage address usually includes the
arithmetic addition of address components (such as base address plus
displacement).  Portions of the address resulting from this addition
are then used to address entries in storage arrays which represent
the implementation of a TLB, CACHE, CACHE DIRECTORY operation, etc.
It is normally faster to perform an addition for only a few bit
positions comprising an address portion than it is to generate the
carry for such a portion.  Therefore, the addition for a few portion
bits can be done twice in parallel by two adders (one assuming a
carry and one assuming no carry), while the actual carry is being
generated which, when available, is used to select one of the two
adder results (carry select adder).  Still, the result of the carry
operation, i.e., the actual carry, is the most recent signal to be
generated and determines the delay of generating an address portion.

      The approach of the proposed scheme is not to wait with address
decoding in a storage array receiving an address portion until the
carry has been generated and used to select the correct adder result
but to provide two word line decoders feeding results in...