Browse Prior Art Database

Logic Facility for Automatic Storage Configuration

IP.com Disclosure Number: IPCOM000101640D
Original Publication Date: 1990-Aug-01
Included in the Prior Art Database: 2005-Mar-16
Document File: 3 page(s) / 96K

Publishing Venue

IBM

Related People

Holm, T: AUTHOR [+5]

Abstract

A computer storage supporting operations within a particular address space comprises one or several storage units (e.g., storage cards). The storage size is variable, and/or upgrades and downgrades are implemented by addition and/or removal of such storage units.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 52% of the total text.

Logic Facility for Automatic Storage Configuration

       A computer storage supporting operations within a
particular address space comprises one or several storage units
(e.g., storage cards).  The storage size is variable, and/or upgrades
and downgrades are implemented by addition and/or removal of such
storage units.

      The physical size of the storage and its topology must be
available to the processing unit for correlating the respective
storage address with the physical storage module and for configuring
it for the address space available.

      The described logic facility is implemented in the storage
control logic and facilitates this configuration during
power-on-reset of the entire system.

      Each storage module supports a configuration input and a
configuration output signal line, and all storage modules are
interconnected (Fig. 1).  The configuration input to the first card
is inactive (floating = positive), whereas the inputs to the
subsequent cards are driven to the active state (negative) by the
previous card.

      The logic used on each card (Fig. 2) consists of
      o    a latch implemented as a shift register latch (SRL);
      o    a binary counter consisting of n stages, where n is the
maximum number of storage modules (binary position counter);
      o    a binary counter with n+1 stages to facilitate the last
card indication, and
      o    a control logic for gating inputs and enabling output
drivers.

      A timing diagram (Fig. 3) shows an implementation of a maximum
of 4 storage modules.

      The whole system is initialized after power-on by shifting an
initial pattern into all latches.  This pattern is...