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CMOS Automatic Performance Level Assignment Algorithm for Computer Aided Circuit Design

IP.com Disclosure Number: IPCOM000101657D
Original Publication Date: 1990-Aug-01
Included in the Prior Art Database: 2005-Mar-16
Document File: 1 page(s) / 36K

Publishing Venue

IBM

Related People

Aipperspach, AG: AUTHOR [+5]

Abstract

An algorithm is designed wherein capacitance loading tables are searched and results applied automatically to select circuit performance along with selection of logic functions (books) instead of applying fixed delay constraints for each book. Books with and without output buffers are supported by this system. A circuit designer can optimize individual outputs by applying FAST, SLOW, or NORMAL instructions.

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CMOS Automatic Performance Level Assignment Algorithm for Computer Aided Circuit Design

       An algorithm is designed wherein capacitance loading
tables are searched and results applied automatically to select
circuit performance along with selection of logic functions (books)
instead of applying fixed delay constraints for each book.  Books
with and without output buffers are supported by this system.  A
circuit designer can optimize individual outputs by applying FAST,
SLOW, or NORMAL instructions.

      The algorithm automatically selects the performance level of a
book based on the total load capacitance (CL), CL = Cwire + Cgate
(where Cwire = wire capacitance and Cgate = gate capacitance), into
which the book is being placed.  A pre-calculated cross-over
capacitance (Cxo) curve for each book is used to judge whether CL
exceeds Cxo.  Performance of the book is increased to a next level
until Cxo is not exceeded.

      Cxo points for each book are based on detailed circuit analysis
to ensure optimal performance with minimum impact to rate of current
change (di/dt).  Overdriving loads can cause a sharp rise in di/dt
and result in excessive noise voltage on a power bus.

      Slow and fast cross-over points may be selected by the designer
which are generally used in critical path design. For instance, to
reduce loading on a critical circuit, slow cross-over points may be
selected.

      This algorithm may be used both before and after physic...