Dismiss
InnovationQ will be updated on Sunday, Oct. 22, from 10am ET - noon. You may experience brief service interruptions during that time.
Browse Prior Art Database

Bus Master Physical Address Services for Personal Computers

IP.com Disclosure Number: IPCOM000101662D
Original Publication Date: 1990-Aug-01
Included in the Prior Art Database: 2005-Mar-16
Document File: 5 page(s) / 197K

Publishing Venue

IBM

Related People

Allran, GG: AUTHOR [+6]

Abstract

A technique is described to provide a protocol which allows virtual memory (VM) operating systems and bus master physical address drivers to function together in the same system.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 26% of the total text.

Bus Master Physical Address Services for Personal Computers

       A technique is described to provide a protocol which
allows virtual memory (VM) operating systems and bus master physical
address drivers to function together in the same system.

      In prior art, some programs, known as VM operating systems,
using the virtual 8086 mode with processors, such as the Intel 80386
or 80486, with paging enabled, program beneath the BIOS layer by
sharing the direct memory access (DMA) controller.  This amounts to
programming the processor in virtual 8086 mode and using the I/O
permission bit map to gain control upon any accesses to the DMA
controller. Specifically, the VM operating system emulates the DMA
function by modifying the linear address that the bus master physical
address driver assumes is a physical address into the correct
physical address (according to the VM operating system).

      This technique of emulating the DMA function only functions for
those devices which use an actual DMA controller.  For bus master
devices, the DMA function of interfacing to system memory is
performed by the bus master device independent of the DMA controller.
The interface in programs to the bus master device is different than
the interface to the DMA controller.  The I/O ports of the DMA
controller are located at differing addresses than the I/O ports of
the bus master device.

      As a result, those VM operating systems that depend on bus
master physical address drivers to use the DMA controller will fail.
The bus master physical address driver will provide what is believed
to be a physical address to the bus master device.  In actuality, in
virtual 8086 mode, what is provided by the bus master physical
address driver is a linear address.  The bus master device will
perform the requested operation and transfer data to the bus master
device from memory or from the bus master device to memory.

      In addition, VM operating systems gain additional information
from devices that use the DMA controller that does not perform the
same for bus master devices.  When a physical address is attempted to
be written to the DMA controller, the VM operating system, using the
exception that is generated by the I/O protection bit map, will
determine that the memory that is being used in a transfer must be
locked or pinned.  The VM operating system will then use the
interrupt from a DMA device on a terminal count to determine that the
DMA device is finished with the memory and the meory can be unlocked
or unpinned.  This unneccessarily ties the unlocking or unpinning
memory to the specific hardware interrupt level of the device.

      The following interface provides a method of solving the above
problem:
      Interrupt 4Bh
      ­ (AH) = 81H - Bus Master Physical Address Services
        This function is defined to be provided by a Virtual-8086
mode operating system and allows the operating system to do two
fun...