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Browse Prior Art Database

Dynamic Scatter Gather Table

IP.com Disclosure Number: IPCOM000101686D
Original Publication Date: 1990-Aug-01
Included in the Prior Art Database: 2005-Mar-16
Document File: 3 page(s) / 112K

Publishing Venue

IBM

Related People

Neel, AF, II: AUTHOR [+3]

Abstract

This article describes a method for use in a computer system to control a data chaining operation by allowing bus masters to use scatter gather with dynamic data chaining.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 52% of the total text.

Dynamic Scatter Gather Table

       This article describes a method for use in a computer
system to control a data chaining operation by allowing bus masters
to use scatter gather with dynamic data chaining.

      The full-scale subsystem control block (SCB) implementation of
reading in the entire SCB table is not practical for many data
rate-dependent applications.  A method is disclosed herein for
providing a non-intelligent bus master the ability to use the scatter
gather data chaining mechanism with a minimum of overhead from
fetching table entries.  Furthermore, the ability to dynamically
update the scatter gather table (SGT) after the non-intelligent bus
master has begun accessing the table is provided.

      The SGT control field fits inside an already established data
chaining architecture.  Instead of a single 32-bit length, the SCB
SGT length field is divided into an 8-bit control field in the most
significant byte and a 24-bit length field in the low-order 3 bytes.
The high-order 3 bits of the control field have been defined as shown
in the drawing.  The remaining 5 bits have been reserved for future
use.

      The device driver/basic input output system (BIOS) allocates
memory for the SGT and initializes the Data Block Ready (DBR) bit to
Not Ready for each table entry.  The Block Interrupt (BINT) and
Reload Table Address (RTA) bits can also be set at this time.  The
device driver/BIOS then begins fetching data from the disk and
writing the data into the data block buffers it has previously
allocated.  After each data block buffer is filled with disk data,
the device driver/BIOS then goes back to the corresponding SGT entry
that points to that data buffer and writes the DBR bit to Data Ready.

      Data fetches by the non-intelligent bus master are initiated by
the device driver/BIOS writing the start address of the SGT to the
SGT start address register inside the bus master.  When the Start
Transfer bit inside the bus master is set active, the start address
register contents are loaded into the current SGT fetch address
register and the bus master can begin reading from the SGT.  The bus
master reads the 32-bit data block address, the 8-bit control byte,
and the 24-bit data block length from the SGT. Before any data is
transferred from the data block, the bus master first checks the DBR
...