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Browse Prior Art Database

New Image Power Distribution

IP.com Disclosure Number: IPCOM000101693D
Original Publication Date: 1990-Aug-01
Included in the Prior Art Database: 2005-Mar-16
Document File: 2 page(s) / 76K

Publishing Venue

IBM

Related People

Lampin, P: AUTHOR [+6]

Abstract

Described below are some special design features that aim to reduce noise in gate arrays chips.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 52% of the total text.

New Image Power Distribution

       Described below are some special design features that aim
to reduce noise in gate arrays chips.

      First of all, no connections are to be made between internal
array supply and IOs supply to induce a better noise decoupling. The
performances of the internal circuits are not degraded by the noise
due to the switching IOs. There is a double ring (GND/VDD) all around
the chip for the IOs supply and another one for the internal array
supply. Next, the tree/grid image for internal array must be mixed.
To have a more regular power distribution for the internal array, the
image has been designed with a grid image concept (small M1 and M2
buses) spread  over the chip by the grid; power distribution has been
strengthened with large M1 and M2 buses designed with a tree concept.
Also, only programmable power IOs have been used. Images have been
designed with no fixed power IOs. All the power IOs are programmable
power IOs and they are preplaced by the user at right locations
according to the chip population. Finally, bus cutting devices are
necessary. Some special devices have been designed to cut the IO
supplying buses in order to isolate quiet IOs from switching IOs.
They have been designed in gate array IO cells and contain a shape
which will cut in the image the M2 buses which supply the IOs all
around the chip. This special shape has been designed on MAC2 level
and is automatically handled by the shape check rule in order to cut
t...