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Current Bias Testing for Memory Cells

IP.com Disclosure Number: IPCOM000101703D
Original Publication Date: 1990-Aug-01
Included in the Prior Art Database: 2005-Mar-16
Document File: 2 page(s) / 47K

Publishing Venue

IBM

Related People

Ho, ST: AUTHOR [+5]

Abstract

Most types of memory cells exhibit a class of defects that do not add a significant delay to read access or write times but instead produce a reduced noise margin on the cell's internal nodes and the bit lines when that cell is read. Typically, there is a probability of detecting these defects dependent on the residual noise margin on the bit lines, the test patterns applied and the tester environment. Since any reduction in noise margin increases the probability of system fails (soft error) and any partial defect shipped also has the potential of becoming a reliability fail, it is desirable to detect these defects. Also certain defects that do produce a delay can be detected more easily (in a static read instead of timed, with a larger delay or at a smaller defect size) by applying test bias.

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Current Bias Testing for Memory Cells

       Most types of memory cells exhibit a class of defects
that do not add a significant delay to read access or write times but
instead produce a reduced noise margin on the cell's internal nodes
and the bit lines when that cell is read. Typically, there is a
probability of detecting these defects dependent on the residual
noise margin on the bit lines, the test patterns applied and the
tester environment.  Since any reduction in noise margin increases
the probability of system fails (soft error) and any partial defect
shipped also has the potential of becoming a reliability fail, it is
desirable to detect these defects.  Also certain defects that do
produce a delay can be detected more easily (in a static read instead
of timed, with a larger delay or at a smaller defect size) by
applying test bias.

      By placing a current source on each bit line, and alternately
turning the left test current source on and then the right test
current source, it is possible to reduce the noise margin on the bit
lines for a non-defective cell (when considering process variation)
without writing it and still reading the correct data.   On a cell
with a noise margin defect, biasing will cause a failure by providing
enough of a voltage differential to overcome the residual noise
margin so the opposite data value is read.

      It is also possible to place test bias current sources in later
stages of differential sense amplifiers to d...