Browse Prior Art Database

ECC Verifier

IP.com Disclosure Number: IPCOM000101705D
Original Publication Date: 1990-Aug-01
Included in the Prior Art Database: 2005-Mar-16
Document File: 2 page(s) / 46K

Publishing Venue

IBM

Related People

Aichelmann, FJ, Jr: AUTHOR

Abstract

A method is proposed for providing a way to detect ECC logic malfunctions. Additionally, this development makes it possible to improve the data integrity of the memory system by being able to verify corrections.

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ECC Verifier

       A method is proposed for providing a way to detect ECC
logic malfunctions.  Additionally, this development makes it possible
to improve the data integrity of the memory system by being able to
verify corrections.

      With conventional ECC facilities, data that has been processed
(i. e., corrected) is assumed to be correct with no further attempt
to determine any malfunctions.  This proposal provides an additional
path after correction has occurred to verify proper operation.  A
malfunction would have occurred after ECC processing if the original
error was not eliminated or the correctable error became
uncorrectable. Individual check bit errors are not treated by the
data-bit modifier of convention ECC facilities.

      Fig. 1 describes a block diagram of conventional ECC facilities
for read operations.  Fig. 2 depicts the modification of conventional
ECC facilities which provides for a verification of correction
operations.  This is accomplished by adding a latch which traps the
original syndromes so that the modified data can be flushed through
the syndrome generation path.  The syndrome match detector checks for
zero syndromes signaling that the proper correction has occurred.