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Method for test pattern compression on automated test equipment

IP.com Disclosure Number: IPCOM000101707D
Publication Date: 2005-Mar-16
Document File: 6 page(s) / 86K

Publishing Venue

The IP.com Prior Art Database

Abstract

Disclosed is a method for test pattern compression on automated test equipment. Benefits include improved functionality and improved performance.

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Method for test pattern compression on automated test equipment

Disclosed is a method for test pattern compression on automated test equipment. Benefits include improved functionality and improved performance.

Background

              The conventional pattern compression technique uses repeating test vectors that rely on all tester channels in the vector to maintain an identical data pattern across multiple vector cycles. This approach saves vector memory usage and minimizes test pattern load time for a small pattern object size. However, with emerging high-speed serial technology, this conventional approach becomes much less effective at handling the huge volume of vector data.  A serial interface generally functions as an independent lane. Compressible pattern sequences across multiple pins are not typical.

General description

      The disclosed method uses a simple vocabulary and look-up technique to perform run-time decompression of the encoded tester pattern stored in a tester’s dynamic random access memory (DRAM). The encoded pattern data contains a key to indicate whether a compressed vocabulary value (look-up index) or uncompressed data follows the key. An assessment of the key value is performed and followed by a look up of compressed or uncompressed data. This approach provides significant savings in the vector memory size, pattern object files size, and pattern load time.   The key elements of the method include:

•             Per-pin application

•             Configurable word length, such as 16, 20, 32, or 40 bits

•             User-specified bit sequence

•             User-specified encoded pattern data key

•             Key that is used as the address field for the look-up table

•             Vocabulary that is created by the pattern compiler

•             Vocabulary that is stored in the pattern object files based on the user’s specification

•             Interleaved DRAM memory reads to fill a fast pattern generator cache or FIFO
     mechanism at runtime

•             Decompression during pattern transfer from DRAM to cache, if the address field for the
     sequence lookup is small enough

 

Advantages

              The disclosed method provides advantages, including:

•             Improved functionality due to compressing on a per-pin basis

•             Improved performance due to detecting more compressible pattern sequences than with
     the conventional method

•             Improved performance due to providing enhanced compression

Detailed description

      The disclosed method is test pattern compression on automated test equipment. The method is embedded in the flow, compiler coding, and the runtime decompressor. A block diagram illustrates the path from DRAM to the pattern cache (see Figure 1).

              The bit-grouping counts for test vectors have some common bit sequences on a per-pin basis. Storing these common sequences in a look-up table and referencing them with a key, such as an address field,...