Browse Prior Art Database

BTRTOGLI - A Structured Logic Placement Program

IP.com Disclosure Number: IPCOM000101710D
Original Publication Date: 1990-Aug-01
Included in the Prior Art Database: 2005-Mar-16
Document File: 2 page(s) / 102K

Publishing Venue

IBM

Related People

Seewann, E: AUTHOR

Abstract

Disclosed is a structured logic placement program that allows both logic file dependent and specifiable and predictable circuit placement. It is particularly useful to build general structured data flow components, such as registers, multiplexers, RAMs, register files, adders, shifters, and the like.

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This is the abbreviated version, containing approximately 52% of the total text.

BTRTOGLI - A Structured Logic Placement Program

       Disclosed is a structured logic placement program that
allows both logic file dependent and specifiable and predictable
circuit placement.  It is particularly useful to build general
structured data flow components, such as registers, multiplexers,
RAMs, register files, adders, shifters, and the like.

      This program differs from "macro generators" in one very
important respect, namely, in that it provides logic file dependent
placement.  Circuit placement for such generators is independent from
the logic file, i.e., they "generate" rather than "place" circuits.
For example, if one adds a circuit to the logic file, a placement
program adds a circuit to the placement, whereas, a macro generator
does not.  Alternatively, circuits can be placed by macro generators
which are not present in the logic file.  Despite this drawback,
macro generators are useful since they at least provide specifiable
and predictable placement.

      The problem with "statistical" placement programs is that
although they do provide logic file dependent placement, they do not
allow predictable and specifiable placement.  Although many of these
programs have a "pre-placement" feature, the fact is that this is not
useful to build general data flow components (i.e., it is easier and
more productive to use a macro generator, or, for that matter, to do
it manually in those cases in which specifiable placement is
required.

      The structured placement program disclosed herein overcomes the
shortcomings outlined above.  In BTRTOGL1 the logic file is equal to
the placement file.  In other words, the structure is assumed by the
program to be inherent in the input circuit (BTR) sequence of the
logic design file. If this sequence is changed, then the placement is
also changed.  If blocks are added to or deleted from the logic file,
then this is also reflected in the placement file. Structural
elements, such as buses, spacers and the like, which are not present
in the logic file are added automatically by the program upon
reaching user specifiable boundary conditions.

      In general, placement is controlled both from the logic file
and a separate rules (GUT) file.  Upon execution, BTRTOGL1 assumes
that the input BTR (circuit or logic file) sequence is a placement
file.  The program reads a block (circuit) from the logic file and
uses the block rule (Brule), block hardware code (BHC), as well as
the current block logical as a search key to find a corresponding GUT
(placement) rule. It then places the block...