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Method for a via-array capacitor on the backside of a space transformer for probe cards

IP.com Disclosure Number: IPCOM000101711D
Publication Date: 2005-Mar-16
Document File: 5 page(s) / 202K

Publishing Venue

The IP.com Prior Art Database

Abstract

Disclosed is a method for a via-array capacitor on the backside of a space transformer for probe cards. Benefits include improved functionality and improved performance.

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Method for a via-array capacitor on the backside of a space transformer for probe cards

Disclosed is a method for a via-array capacitor on the backside of a space transformer for probe cards. Benefits include improved functionality and improved performance.

Background

      Power delivery and mechanical rigidity are expected to increase as concerns about microprocessor wafer-level testing.

              CPU power consumption increases as more transistors are used per die. As a result, the CPU operating frequency increases and the operating voltage drops. High current is required in a very short period of time (high di/dt). This trend poses a big VCC droop gap for probe card’s power delivery. Failure to address the power delivery problem may result in unfavorable wafer test results, such as a lower maximum frequency, longer test time, and lower yield.

      The conventional probe-card space transformer decoupling scheme uses discrete capacitor components in an array pattern. A keep-out region has no points for mechanical contact or electrical (power and ground) interconnects available to support the land side of the space transformer during wafer testing (see Figures 1 and 2).

      Previous mechanical modeling simulations indicate significant reduction in mechanical deflection within the die footprint when mechanical support is provided at the center of the probe card. However, due to a higher priority for meeting electrical demands, the keep-out area is maintained to prevent mechanical hardware support from depopulating the capacitor-array pattern (see Figures 3 and 4).

              To address the power delivery issue, the conventional space-transformer decoupling scheme uses a number of low ESL capacitors (i.e. 8-terminal IDC) with no interconnect support available on the backside of the capacitor body. They have pads on one side and a keep-out zone on the side capacitors. As a result, little to no mechanical support is provided against the probe force in the die area.

General description

      The disclosed method is the probe card architecture with a via-array decoupling capacitor and an associated interconnect structure on the backside of a space transformer. The key elements of the disclosed method include the following:

•             Via-array capacitor

•             Controlled collapse chip collect (C4) bumps and pads on both sides of the space transformer for probe card applications

•             Modified interconnect structure to provide mechanical support and make electrical contact on all landside pads

Advantages

              The disclosed method provides advantages, including:

•           ...