Browse Prior Art Database

Resistive Pull-Up Cascode Sense Amplifier

IP.com Disclosure Number: IPCOM000101721D
Original Publication Date: 1990-Aug-01
Included in the Prior Art Database: 2005-Mar-16
Document File: 2 page(s) / 38K

Publishing Venue

IBM

Related People

Dervenis, JP: AUTHOR

Abstract

Disclosed is a sense amplifier used primarily to determine if a cell of an array contains a logic "1" or a logic "0."

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This is the abbreviated version, containing approximately 100% of the total text.

Resistive Pull-Up Cascode Sense Amplifier

       Disclosed is a sense amplifier used primarily to
determine if a cell of an array contains a logic "1" or a logic "0."

      Depending on the contents of the cell, current will be drawn
from either the left bit line (LBL) or the right bit line (RBL), thus
creating a differential voltage between these two bitlines (see the
figure). This differential is input into a Current Switch Emitter
Follower (CSEF) after being shifted down via resistors R1 and R2 and
constant current sources J1 and J2.  If LBL is at a higher voltage
than RBL, the outputs OUT and OUTN will be at logic "0" and "1,"
respectively.  The reverse is true if RBL is at a higher voltage than
LBL.

      During this normal read operation, the Data Out Gate (DOG)
input of transistor T6 is at a lower voltage than constant input VR
of transistor T5.  When the output OUT is to be set to logic "0,"
irrespective of the cell contents, the DOG input switches to a
voltage higher than that of VR. The switching of the DOG input causes
the bitlines to glitch; however, this does not penalize the
associated delays between the DOG input and the outputs OUT and OUTN,
since the DOG input is compared to a constant input VR, by using a
second stage CSEF, called cascoding.