Browse Prior Art Database

Preemptible Cache Line Prefetch Algorithm And Implementation

IP.com Disclosure Number: IPCOM000101722D
Original Publication Date: 1990-Aug-01
Included in the Prior Art Database: 2005-Mar-16
Document File: 3 page(s) / 126K

Publishing Venue

IBM

Related People

Bakoglu, HB: AUTHOR

Abstract

There are advantages and disadvantages for long and short cache lines, and selecting a cache line size is always a compromise. This article describes a preemptible cache line prefetch algorithm and an implementation that combines the advantages of long and short cache lines and eliminate the need for a compromise.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 45% of the total text.

Preemptible Cache Line Prefetch Algorithm And Implementation

       There are advantages and disadvantages for long and short
cache lines, and selecting a cache line size is always a compromise.
This article describes a preemptible cache line prefetch algorithm
and an implementation that combines the advantages of long and short
cache lines and eliminate the need for a compromise.

      Advantages of long cache lines:
      1.   Significantly better hit ratios than short cache
           lines, because when a long line is brought into
           the cache, there is a good chance that
           instructions/data that will be needed shortly are
           brought in, which reduces the number of cache
           misses.  This is based on the principle of
           locality on which the whole idea of caches is
           based.
      2.   Smaller cache directories.

      Disadvantages of long cache lines:
      1.   When a long cache line is brought from memory,
           there is a chance that instructions/data are
           brought in that will not be used.  The main
           disadvantage of this is that the memory bus is
           occupied unnecessarily preventing others from
           using the bus (e.g., D-cache reloads and store
           backs that take many cycles may conflict with
           I-cache reloads).
      2.   Long cache lines make a store through D-cache
           unattractive.  If a long cache line is sent to
           memory every time a store is executed, the memory
           bus utilization will increase dramatically.  The
           entire line needs to be sent to memory even if
           only a small portion of it is modified, occupying
           the memory bus unnecessarily.

      Advantages of short cache lines:
      1.   Shorter cache lines take less time to transfer.
           Only what is needed is transferred and the bus is
           not occupied unnecessarily.  This is very
           important in applications where the memory
           bandwidth is stressed.  This is true especially in
           tightly-coupled multiprocessors.  That is why
           tightly-coupled multiprocessors generally have
           short cache lines (typically, one word).
      2.   Short cache lines make a store-through data cache
           feasible without increasing the memory bus
           utilization too much that would have degraded the
           performance excessively.  To ensure cache
           consistency without making the hardware extremely
           complicated, some tightly-coupled multiprocessors
         ...