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CMOS Selectable Nand-Nor Circuit

IP.com Disclosure Number: IPCOM000101727D
Original Publication Date: 1990-Aug-01
Included in the Prior Art Database: 2005-Mar-16
Document File: 3 page(s) / 102K

Publishing Venue

IBM

Related People

Oakland, SF: AUTHOR

Abstract

A high-density and efficient CMOS selectable NAND-NOR circuit is shown. The disclosed circuit is useful in binary up-down counter circuits and may be useful in other applications, such as an arithmetic unit.

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This is the abbreviated version, containing approximately 52% of the total text.

CMOS Selectable Nand-Nor Circuit

       A high-density and efficient CMOS selectable NAND-NOR
circuit is shown.  The disclosed circuit is useful in binary up-down
counter circuits and may be useful in other applications, such as an
arithmetic unit.

      In a binary up-down counter it is necessary to detect all ones
when counting up, and it is necessary to detect all zeros when
counting down. Since the NAND function has a unique response to the
all-ones condition, and since the NOR function has a unique response
to the all-zeros condition, it is necessary to select between the
NAND and NOR function depending on whether the counter is counting up
or down.

      Methods of selecting between NAND and NOR logic functions when
counting up (NAND) or down (NOR) in a conventional binary synchronous
up-down counter are slow. By imbedding the select function within the
same circuits as the NAND and NOR functions, a faster performance is
achieved while using fewer transistors.

      Referring to Fig. 1, a selectable n-Way NAND-NOR circuit where
the output is shown by equation:

                            (Image Omitted)

 O =   {(( D)&(B0&...&Bn-1)) ¯ (D&(B0¯...¯Bn-1))}
where    is the logic NOT operation,
       &  is the logic AND operation,
       ¯  is the logic OR operation,
       Bj is the jth bit of the counter (for j=0,1,...,n-1),
       D  is the control signal, i.e., 0 when counting up, 1 when
counting down.
The circuit consists of
the series connection of n N-channel MOSFETs (1)
the series connection of an equal number of P-channel MOSFETs (2)
the parallel connection of the same number of N-channel MOSFETs (3)
the parallel connection of the same number of P-channel MOSFETs (4)
a select P-channel device (5), and
a select N-channel device (6).

      Referring to Fig. 2, a selectable 3-Way NAND-NOR is shown where
the output is shown by equation:
                O =   {(( D&(B0&B1&B2))¯(D&(B0¯B1¯B2))}

      When select input D is 1, select P-channel device (5) is off,
preventing the parallel connection of P-channel MOSFETs (4) from
affecting the output node (O). The series connection of P-channel
MOSFETs (2) is connected between VDD and the output node (O);
whenever all inputs B0 ... Bn-1 are 0, this connection pulls the
output node to 1 (VDD). The par...