Browse Prior Art Database

Flexible System Bus Structure With Programmable Transfer Speeds

IP.com Disclosure Number: IPCOM000101728D
Original Publication Date: 1990-Aug-01
Included in the Prior Art Database: 2005-Mar-16
Document File: 3 page(s) / 91K

Publishing Venue

IBM

Related People

Bakoglu, HB: AUTHOR [+3]

Abstract

As the CPU clock frequency improves, it becomes more difficult to keep the system bus running synchronously with the CPU. A typical system configuration is shown in Fig. 1. The region that runs synchronously is shaded.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 56% of the total text.

Flexible System Bus Structure With Programmable Transfer Speeds

       As the CPU clock frequency improves, it becomes more
difficult to keep the system bus running synchronously with the CPU.
A typical system configuration is shown in Fig. 1. The region that
runs synchronously is shaded.

      To avoid limiting the cycle time due to the large electrical
loading on the SIO bus the following approach is proposed:
      A.   The system bus should be separated into a memory bus and a
system I/O (SIO) bus.
      B.   The clock on the memory bus and the system I/O bus should
be independent from the CPU clock.

      If the memory and system I/O clocks are the same as the CPU
clock, there are two options when the system bus becomes the cycle
time limiting factor:
      1.   Let the system bus dictate the CPU clock frequency.  This
is unacceptable because of performance reasons.  The CPU should not
be slowed down because of the system buses.
      2.   Run the system bus at half the frequency of the CPU clock
frequency.  That is, have a data transfer on the system bus every
other CPU clock cycle.  This is more acceptable than option 1, but it
still has adverse performance consequences because as the CPU gets
faster, at one point, the system bus bandwidth goes down by a factor
of two.

      The solution to this problem, as described in this article, is
to run the system buses asynchronously from the CPU.  Fig. 2
illustrates the se...