Browse Prior Art Database

Method for a dice before-grind die-preparation assembly process for 3-D stacked wafers

IP.com Disclosure Number: IPCOM000101730D
Publication Date: 2005-Mar-16
Document File: 4 page(s) / 150K

Publishing Venue

The IP.com Prior Art Database

Abstract

Disclosed is a method for a dice before-grind die-preparation assembly process for three dimensional (3-D) stacked wafers. Benefits include improved functionality and improved yield.

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Method for a dice before-grind die-preparation assembly process for 3-D stacked wafers

Disclosed is a method for a dice before-grind die-preparation assembly process for three dimensional (3-D) stacked wafers. Benefits include improved functionality and improved yield.

Background

      The individual dies of 3-D stacked wafers must be singulated in the die preparation module before being attached to the substrate. The conventional die singulation process includes the following steps (see Figure 1):

1.   Wafer mounting

2.   Wafer sawing
3.           Tape and reel sorting

      These steps result in significant chipping and edge damage due to the small gap between the two bonded wafers. The damage can proliferate into the active thin films, resulting in delamination of the dielectric materials.  No conventional solution to this problem exists today.

General description

      The disclosed method is die preparation and singulation of 3-D stacked wafers. Mechanical saw or laserscribe creates a 100um deep trench into the front of both wafers prior to wafer bonding.  During the trenching process all of the device layers are removed from the die streets to prevent potential thermal and mechanical damage during the final singulation process.  After partially dicing the wafers, the two wafers are bonded together and singulated using a rotary diamond saw.

      When processing is completed on the top wafer, the wafer stack contains the following items (see Figure 2):
•             Controlled collapse chip collect (C4) input/output solder bump

•             Through-silicon vias
•             Thinned top wafer
•             Copper-to-copper diffusion bonded interface

•             Full-thickness bottom wafer

Advantages

              The disclosed method provides advantages, including:

•             Improved functionality due to performing scribing and partial cutting before backgrinding and singulation

•             Improved yield due to minimizing damage from thermal and mechanical damage from singulation

Detailed description

      The disclosed method includes die preparation and singulation of 3-D stacked wafers. A dicing saw partially cuts the streets of both the top and bottom wafers. The partial cut appears as a groove. After partial dicing of both wafers they are bonded together.  The grinder then thins the back of the top wafer and eventually reaches the partial cut depth. When this occurs, the top wafer separates into individual devices although still bonded to the bottom wafer. After the devices are transferred onto tape and a frame, a narrow blade saw process is used to singulate the bottom wafer without contacting the active devices layers which were removed from the streets during the partial dicing processes.  The final singulation process step only interacts with the full-thickness bottom wafer, enabling the use of conventional rotary blade singulation. The process can be easily optimized to minimize chipping and mechani...