Browse Prior Art Database

Flexible Redundancy for VRAM With Split Register

IP.com Disclosure Number: IPCOM000101731D
Original Publication Date: 1990-Aug-01
Included in the Prior Art Database: 2005-Mar-16
Document File: 2 page(s) / 71K

Publishing Venue

IBM

Related People

Hiltebeitel, N: AUTHOR [+4]

Abstract

A video RAM (VRAM) with column (bit) redundancy and split register operation is controlled so as to allow flexibility in assigning redundant elements to either half of the split register.

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Flexible Redundancy for VRAM With

Split

Register

       A video RAM (VRAM) with column (bit) redundancy and split
register operation is controlled so as to allow flexibility in
assigning redundant elements to either half of the split register.

      A system is shown for an improved data transfer control system
used to refresh video screens. A conventional dynamic random-access
memory (DRAM) with column (bit) redundancy and a serially addressable
split register is utilized to create a seamless serial bit stream.
With a few additional control circuits, flexible column (bit)
redundant assignments between the two halves of the serially
addressed split register are accommodated. The new method utilizes
current column redundancy control circuitry and a few additional
circuits to create an efficient column (bit) redundant assignment
scheme.

      Fig. 1 shows the true/complement (TC) gate 2, bit redundancy
fuses and latches 6, primary port address compare 4, and serial
address compare 8. There is one TC gate per address per chip except
for the most significant TC. There is one block 4, 6, 8 per redundant
element. This circuitry may be located anywhere on the chip. Signal
MATCH is a buffered signal that goes to the local redundant circuit
shown in Fig. 2.

      During a normal primary port read or write cycle, all of the
transfer signals are low. This opens 2 and 14. The TCs are allowed to
pass on to 4 and the match signal is allowed to pass through 14.
During...