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Liquid Crystal on Silicon Stacked Mixed Technology Package for a Two-Die Solution

IP.com Disclosure Number: IPCOM000101740D
Publication Date: 2005-Mar-16
Document File: 2 page(s) / 99K

Publishing Venue

The IP.com Prior Art Database

Abstract

Disclosed is a method that applies a mix of flip-chip and wire bonding package technologies on liquid crystal on silicon (LCoS) packaging. Benefits include reducing demands on the size of the substrate.

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Liquid Crystal on Silicon Stacked Mixed Technology Package for a Two-Die Solution

Disclosed is a method that applies a mix of flip-chip and wire bonding package technologies on  liquid crystal on silicon (LCoS) packaging. Benefits include reducing demands on the size of the substrate.

Background

The cost of LCoS packaging for multiple die applications is very high. Today’s estimates show that these package substrate costs can be as much as 30-40% of the overall device costs. Currently, if multiple dies are needed, the only option is to increase the size of the substrate, which increases costs. This may warp the imager beyond 1-2um and distort the images; this can further drive up costs by requiring elaborate solutions (e.g. silicon or glass mesas) or by using very expensive substrate technologies (see Figure 1).

General Description

The disclosed method applies other technologies to a new application space. The mixed technologies (e.g. a combination of flip-chip and wire bond) approach allows for the use of a lower cost substrate (see Figure 2). The disclosed method flip-chips the frame buffer using a standard flip-chip process technology (see Figure 3), then attaches the imager die on top of the die, and uses the frame buffer as a CTE interposer for the imager die. If a low cost substrate is used, the flip-chip die is somewhat warped when cooled to room temperature, but this should not be an issue when the die attach material is applied; it handles any discrepancies and a...