Browse Prior Art Database

High-Speed Programmable Frequency Checker

IP.com Disclosure Number: IPCOM000101752D
Original Publication Date: 1990-Aug-01
Included in the Prior Art Database: 2005-Mar-16
Document File: 8 page(s) / 277K

Publishing Venue

IBM

Related People

Blair, JD: AUTHOR [+3]

Abstract

This article describes a high-speed frequency checker which can be used to perform the frequency-limiting function for high-speed communication systems. It can be programmed to operate at different speeds and frequency tolerances.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 28% of the total text.

High-Speed Programmable Frequency Checker

       This article describes a high-speed frequency checker
which can be used to perform the frequency-limiting function for
high-speed communication systems.  It can be programmed to operate at
different speeds and frequency tolerances.

      In a typical synchronous communication logic design, there are
two critical parameters which affect the accuracy of the overall
system.  First, the recovered clock has to be synchronous with the
recovered data.  Second, the recovered clock frequency must not drift
above the performance limit of the logic technology used in the
hardware.

      The most critical condition is when the recovered clock
frequency of the system is very close to the maximum performance
limit of the logic technology used in the design.  To ensure that the
recovered clock is within the system tolerance, and the clock
frequency is operating within the performance region of the logic
technology, a high-speed frequency checker is described.  This
high-speed frequency checker can be software programmed to operate at
different speeds (in the example described in this disclosure, the
speed of the frequency checker can be programmed to work at 4 Mbps or
16 Mbps).  The frequency error detector used for this frequency
checker is designed in such a way that it can detect frequency error
much faster than a conventional detector.  This fast detection design
also increases the sensitivity and responsiveness of the adapter's
frequency monitoring system.  To demonstrate the operation of the
frequency checker, the following paragraphs describe a frequency
monitoring system.

      Fig. 1 is a system block diagram of a frequency monitoring
system.  It consists of a High-Speed Programmable Frequency Checker
(HSPFC), a Phase-Locked Loop (PLL), a Voltage-Controlled Oscillator
(VCO) and a PLL Reference Selector.

      During operation, the HSPFC continuously compares the frequency
of the recovered VCO clock with that of the local crystal oscillator
(XTAL clock).  If the recovered clock frequency ever drifts above a
predeter mined tolerance, the HSPFC would send a "frequency error"
signal to the PLL Reference Selector to select the crystal clock as
the PLL reference input.  This will ensure the PLL to lock back on
the local crystal clock instead of continuously drifting off in
frequency.  Also, the HSPFC is designed to be programmable to operate
at both 4 Mbps and 16 Mbps.

      Fig. 2 is a block diagram of the High-Speed Programmable
Frequency Checker (HSPFC).  It comprises a basic reset counter, a
source counter, a sink counter, a source/sink comparator, a
high-speed pulse sampler, and a counter reset control block.  The
increment clock of the source counter and the basic reset counter are
driven by the recovered VCO clock.  The increment clock of the sink
counter is driven by the local crystal clock.  Since the source
counter and the sink counter are operating...