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Tie Bar-Less and Bus-Less PBGA Substrate for Two-Layer and Multi-Layer Build-Up

IP.com Disclosure Number: IPCOM000101770D
Publication Date: 2005-Mar-16
Document File: 3 page(s) / 251K

Publishing Venue

The IP.com Prior Art Database

Abstract

Disclosed is a method that eliminates the plating tie bar and plating bus line to increase the available space on the substrate for the high-density and compact designs of two-layer and multi-layer PBGA substrates. Benefits include enhanced reliability and electrical performance.

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Tie Bar-Less and Bus-Less PBGA Substrate for Two-Layer and Multi-Layer Build-Up

Disclosed is a method that eliminates the plating tie bar and plating bus line to increase the available space on the substrate for the high-density and compact designs of two-layer and multi-layer PBGA substrates. Benefits include enhanced reliability and electrical performance.

Background

More space is needed for bus lines; however, this restricts high-density or compact designs and small form factor packages (see Figure 1). To accommodate the bus lines, plating tie bars and bus lines are present in the substrate area. The package design may use a tie bar-less area, however the bus lines still remain. It is possible to achieve a tie bar-less and bus-less area, but all of the conductive traces are covered with gold, which is used as a copper etch resist. The dangle of gold on top of the copper trace is prone to wire bond finger collapse. Also, it is expensive to create the fully gold-plated pattern.

General Description

The disclosed method does not have plating tie bars and plating bus lines within the substrate foot print (see Figure 2). The plating tie bars and bus lines are eliminated during the substrate fabrication process in order to free up the substrate’s real state for high density and compact designs, which are applicable for two-layer and multi-layer substrate layer counts. The disclosed method enhances electrical performance, increases reliability, and allows for smaller and thinner package dimensions. The following are the key elements of the disclosed method:

Triple imaging process

The disclosed method uses a triple imaging process during the substrate fabrication, where the first photo-resist imaging process creates the conducting line patterns on the wire-bond side of the copper clad laminated panel. The second imaging process creates the opening area for conventional electrolytic nickel/gold plating onto the specific areas; the third imaging proce...