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Mechanism for Shared Access to High-Speed TDM Network Interface

IP.com Disclosure Number: IPCOM000101778D
Original Publication Date: 1990-Aug-01
Included in the Prior Art Database: 2005-Mar-16
Document File: 3 page(s) / 142K

Publishing Venue

IBM

Related People

Davis, GT: AUTHOR [+6]

Abstract

This article describes a circuit arrangement which extends the capability of channel processing on a single time division multiplex (TDM) network interface (I/F) by allowing multiple digital signal processing (DSP) adapter cards to share that common network interface.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 52% of the total text.

Mechanism for Shared Access to High-Speed TDM Network Interface

       This article describes a circuit arrangement which
extends the capability of channel processing on a single time
division multiplex (TDM) network interface (I/F) by allowing multiple
digital signal processing (DSP) adapter cards to share that common
network interface.

      Any adapter card which interfaces to such TDM network
interfaces can process the data transmitted and received via this
interface.  Since the data in each channel or time-slot can represent
analog signals, processing requirements for some applications can be
very extensive, requiring more than that available from a single
card, thus establishing the requirement for a shared network
interface.

      Each of these attachment cards provides a transformer coupled
analog interface which supports both transmit and receive on a
T-1/CEPT-30 line.  Interface circuitry involved includes a clock
extraction circuit which provides the capability to synchronize the
card processing with the received bit rate as well as timing for the
transmit signal. Also included is a line driver and differential
receiver compatible with the required bipolar pulse formats.  The
entire analog interface is powered down unless the interface enable
pin in the interface connector is pulled low.  To activate the analog
interface, this pin may be grounded via a jumper in the interface
connector.

      In order for multiple cards to share a common network
interface, one card must be designated as the master interface to the
TDM carrier.  This master card must be jumpered to enable the
interface while the interfaces of secondary cards remain inactive due
to the absence of a jumper at the interface enable pin.  A secondary
interface is connected between the master card and multiple secondary
cards which allows multiple processing units to share the one active
network interface.

      The drawing illustrates the details of this secondary
interface.  The master card provides a receive clock, transmit clock,
transmit frame synchronization pulse, and receive serial bitstream
positive and negative pulses to all secondary cards via this
secondary interface.  These lines are bidirectional (direction
controlled by interface enable).  Thus, all cards are kept
synchronized to the same frame timing.  In order to allow each card
to control its own designated time-slots in the transmit serial
bitstream, this line is wired as a daisy-chain with the master card
being the last one in the chain.  Each card supplies data to its
transmit serial bitstream output (TSEROUT) for time-slots under its
control.  During time-slots not controlled by that card, a
multiplexer (MUX) will gate the daisy-chained transmit bit-stream
(TSERIN) wire...