Browse Prior Art Database

Efficient Scheme to Reduce Over-Prefetching of Instructions For Loading an Instruction Buffer

IP.com Disclosure Number: IPCOM000101779D
Original Publication Date: 1990-Aug-01
Included in the Prior Art Database: 2005-Mar-16
Document File: 3 page(s) / 104K

Publishing Venue

IBM

Related People

Dodds, SD: AUTHOR [+4]

Abstract

This article describes a technique and hardware to eliminate instruction prefetching from memory in a microprocessor system following an unconditional branch instruction implementable at the memory controller.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 52% of the total text.

Efficient Scheme to Reduce Over-Prefetching of Instructions For Loading an Instruction Buffer

       This article describes a technique and hardware to
eliminate instruction prefetching from memory in a microprocessor
system following an unconditional branch instruction implementable at
the memory controller.

      In order to improve the efficiency of fetching instructions
from memory in a microprocessor system, it is common practice to
prefetch consecutive instructions and store them in an instruction
buffer.  This enables the microprocessor to fetch the first
instruction from the low speed memory and the consecutive
instructions from the high speed instruction buffer.  However, this
prefetching scheme induces unnecessary memory accesses following
unconditional branch instructions which decreases the availability of
memory for other microprocessor system components like direct memory
access (DMA) controllers.  The technique and hardware disclosed
herein solves the problem of over prefetching of instructions while
loading the instruction buffer.

      The scheme of this disclosure utilizes an instruction buffer
valid address range comparator, a prefetch address generator, an
unconditional branch detector, an instruction buffer, an address
multiplexer (MUX) to the memory, and an instruction MUX to the
microprocessor, as shown in the drawing.

      An instruction buffer valid address range comparator compares
the requested instruction's address with the valid address range of
the instruction buffer.  The result of the comparison is used to
control two MUXes, and to inform the prefetch address generator when
to generate the prefetch addresses.  The prefetch address generator
will provide the instruction address during instruction prefetching.
The unconditional branch detector is used to detect an unconditional
branch instruction from the memory.  The instruction buffer is used
to store the prefetched instructions.  The address MUX is used to
select the address either from the microprocessor or from the
prefetch address generator; this address is sent to memory.  The
instruction MUX is used to select the instruction eith...