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Browse Prior Art Database

Timing Generator With High Duty Cycle

IP.com Disclosure Number: IPCOM000101789D
Original Publication Date: 1990-Sep-01
Included in the Prior Art Database: 2005-Mar-16
Document File: 3 page(s) / 75K

Publishing Venue

IBM

Related People

Freeman, LB: AUTHOR [+3]

Abstract

A clock chopper for use in semiconductor devices has been designed with fast recovery time and high duty cycle. In the proposed circuitry, the clock chopper delay path is itself chopped to reset the delay path faster.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 56% of the total text.

Timing Generator With High Duty Cycle

       A clock chopper for use in semiconductor devices has been
designed with fast recovery time and high duty cycle.  In the
proposed circuitry, the clock chopper delay path is itself chopped to
reset the delay path faster.

      In conventional clock choppers, a delay element in one of the
parallel paths is used to generate a pulse whose width is determined
by the length of the delay element.  In these instances the delay
block must be reset before another triggering input, with the reset
time equaling the delay of the block.  Hence, the generated pulse
must be less than half the cycle time to allow for the clock chopper
to recover before the end of the cycle.  This may create difficulties
in the designing and application of the chopper as a whole.

      It is often desirable to have a pulse wider than half the cycle
time.  A circuit (Fig. 1) has been proposed to generate such a pulse.
It consists of three elements: 1) clock stretcher and fast reset, 2)
the delay element, DEL, and 3) an output NOR gate.  The circuit uses
the window between the trailing edge of the longest generated pulse
to the end of the cycle to reset the clock chopper.

      The contents of the clock stretcher and fast reset block of
Fig. 1 are shown in Fig. 2.  This is basically a 2-input NOR gate
with a single emitter follower output driving the DEL block and 7
parallel emitter follower outputs connecting as emitter dots into the
delay...