Browse Prior Art Database

Channel Bidirectional State Machine

IP.com Disclosure Number: IPCOM000101798D
Original Publication Date: 1990-Sep-01
Included in the Prior Art Database: 2005-Mar-16
Document File: 4 page(s) / 155K

Publishing Venue

IBM

Related People

Granato, S: AUTHOR

Abstract

The problem is the operation and checking of Side B (channel side) of the bidirectional (Bi-Di) bus. The problem is solved with the following new state machine structure and method of checking. This structure lends itself to this method of checking which produces a very high degree of error detection.

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This is the abbreviated version, containing approximately 45% of the total text.

Channel Bidirectional State Machine

       The problem is the operation and checking of Side B
(channel side) of the bidirectional (Bi-Di) bus.  The problem is
solved with the following new state machine structure and method of
checking.  This structure lends itself to this method of checking
which produces a very high degree of error detection.

      Incoming information from the Bi-Di is put into a Receive
Platform register.  It is this register that is examined to determine
what was on the Bi-Di last cycle in order to decide what to gate onto
the Bi-Di this cycle (see Fig. 1).

      The state machine which operates the Bi-Di implements the
protocol.  Communication from the channel end is divided into the
Idle/Request, Instruction, Data Transfer, and Blank cycles.  Since
information for the Instruction and Data Transfer cycles comes from
18 registers, the information is pre-loaded into a Platform Out
register.  This register is gated onto the Bi-Di by the state machine
at the appropriate cycle.  The state machine is divided into the
following major states:
   STATE0 - Idle/Request
   STATE1 - Instruction
   STATE2 - Data Transfer
   STATE3 and STATE4 - Handle the Extend Command reception and
interpretation.
   STATE5 - Response to timer update which is hardware initiated.  Do
not want to disturb registers that microcode may be using.
   STATE6 - For putting information in the Bi-Di during data transfer
where, for timing restrictions, the 'normal' STATE2 method cannot be
used.

      The Data Transfer state (STATE2) includes data movement on the
Bi-Di, and blanks.  Since there are many types of data transfer, an
additional register is used, called CYCLE, and decoded to define the
individual data transfer state of each type of transfer.  Data
transfer can occur with the double word data register, the double
word storage command register, or the data array.  The instruction
comes from the instruction register.  All of these storage areas can
be modified by microcode, when the state machine is not using them.

      The state machine operation is indicated to microcode through a
set of SRLs that operate the branch points and traps.  Since
microcode can modify the instruction register any time after it is
sent (to prepare for the next operation), the type of instruction is
decoded during the cycle that the instruction is placed on the Bi-Di
(STATE1).  A path through the state machine is then chosen, the
appropriate value is set into the CYCLE register, and the state
machine moves to the data transfer state (STATE2).  Since there are
17 sources and 9 sinks for data transfer, the use of CYCLE and the
concept of several paths facilitate gating.  For the most part, a
given value of CYCLE will unconditionally step the register to the
next appropriate value in the sequence.  At the completion of the
instruction, all paths return to the IDLE state (STATE0).

      In the data transfer state, the...