Browse Prior Art Database

Register Management for Multiple Decode

IP.com Disclosure Number: IPCOM000101815D
Original Publication Date: 1990-Sep-01
Included in the Prior Art Database: 2005-Mar-16
Document File: 4 page(s) / 151K

Publishing Venue

IBM

Related People

White, SW: AUTHOR

Abstract

An improved register management method is described. The proposed method increases performance when attempting to decode/issue two instructions per cycle and is easy to expand to N at a time decode.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 51% of the total text.

Register Management for Multiple Decode

       An improved register management method is described.  The
proposed method increases performance when attempting to decode/issue
two instructions per cycle and is easy to expand to N at a time
decode.

      Prior-art methods divide fixed-point registers into two groups:
the even numbered registers and the odd numbered registers.  To each
set is assigned a Decode Register Assignment List (DRAL) which maps
architected registers to the physical registers (see Fig. 1).  To
decode two (fixed-point) instructions per cycle, the current design
requires that the two destination register fields must specify
registers which are not in the same register set. With this
restriction, only one entry per DRAL per cycle need be made.

      When two instructions are decoded, one unassigned physical
register is assigned to each of the architected destination
registers.  The two physical register tags are selected by
investigating a set of "ASSIGNED" bits, each bit being associated
with a specific physical register.  The bits associated with the two
newly assigned physical registers are set to indicate that they are
no longer available.  Each of these physical register addresses are
written into the appropriate DRAL.

      Concurrently, the source register fields are used as DRAL
indexes to determine the tags of the physical registers which
"currently" contain the data for the architected source registers.
Each of new instructions, containing an operation code, a destination
tag, and the source register tags, are placed in a different queue,
one queue for each of the functional units.

      As an instruction completes, a "LOADED" bit, associated with
the destination register, is set indicating that the data is
available.  An instruction in a queue is dispatched to the respective
execution unit when all of the LOADED bits, corresponding to the
instruction's source registers, are set.

      The proposed design allows decoding two (or N) instructions
every cycle.  Although this approach could also be used with the
scalar floating point unit(s), this article will consider only the
scalar fixed-point operations.  As illustrated in Fig. 2, it will
partition physical registers (and the associated LOADED and ASSIGNED
bits), rather than architected registers.  As a result, no
restriction will be placed on the relationship of the decoded
destination registers.  The proposed design differs from the prior
art in the design of the physical registers, the LOADED bits, the
ASSIGNED bits, the FREE (UNASSIGNED) tag selection process, and the
DRAL operation.  The differences in operation are described below.

      As the architected fixed-point registers are now in one set, a
single multiple-entry per cycle DRAL is required. Presently, many
(fixed-point and floating-point) registers are implemented using
storage arrays which allow two simultaneous stores along with a
single load.  These...