Browse Prior Art Database

Method to Scan a Dual-Clocked LSSD Design

IP.com Disclosure Number: IPCOM000101821D
Original Publication Date: 1990-Sep-01
Included in the Prior Art Database: 2005-Mar-16
Document File: 3 page(s) / 88K

Publishing Venue

IBM

Related People

Arroyo, RX: AUTHOR [+2]

Abstract

Disclosed is a clock circuit to facilitate diagnostic scanning of a dual-clocked LSSD design with only one of the clocks. This is accomplished by temporarily operating the entire chip off one clock while diagnostic operations are in progress and then returning to the normal dual-clock mode afterwards.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 65% of the total text.

Method to Scan a Dual-Clocked LSSD Design

       Disclosed is a clock circuit to facilitate diagnostic
scanning of a dual-clocked LSSD design with only one of the clocks.
This is accomplished by temporarily operating the entire chip off one
clock while diagnostic operations are in progress and then returning
to the normal dual-clock mode afterwards.

      Fig. 1 shows the block diagram of the clock circuit disclosed.
In this particular LSSD design, each clock cycle is divided into 4
separate phases labeled K0, K1, K2, and K3 for the system clock and
K0', K1', K2', and K3' for the secondary clock.  During normal
operation, the Select Input to the K-CLOCK MUX is 0 which selects the
secondary clock for part of the chip.  During diagnostic operation,
the Select input is set to 1 which selects the system clock for the
entire chip.

      The activation of the UNICLOCK signal indicates the beginning
of a diagnostic operation.  In order to prevent any glitches on LSSD
clocks, the hardware first stops the secondary clock and then
multiplexes in the system clock. When the UNICLOCK signal is
deactivated, the same procedure is followed except that the secondary
clock is multiplexed back in.  The signal UNICLOCK is clocked off the
system clock.

      Fig. 2 is a detailed diagram of the circuit inside the
SWITCHING LOGIC block of Fig. 1. In normal operation, the UNICLOCK
signal is 0 which forces the SELECT signal to a 0. This causes the
MUX to select the secondary...