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Mechanism for Integrating Synchronization And Communication Using Snoopy Cache

IP.com Disclosure Number: IPCOM000101822D
Original Publication Date: 1990-Sep-01
Included in the Prior Art Database: 2005-Mar-16
Document File: 3 page(s) / 107K

Publishing Venue

IBM

Related People

Matsumoto, T: AUTHOR [+4]

Abstract

A mechanism for efficiently performing inter-processor synchronization and communication on a shared-memory, shared-bus multiprocessor system is described. Adding an extra synchronization bit to every word in shared memory, where this bit is cached together with the word, and using all-read and all-write protocols of snoopy cache achieve syn chronization and communication in an integrated manner, not as separate mechanisms. Since this mechanism assumes single-assignment rule for memory words used for synchronization and communication, and is expected to consume a large number of such words, a mechanism for quickly reusing such words is also described.

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Mechanism for Integrating Synchronization And Communication Using Snoopy Cache

       A mechanism for efficiently performing inter-processor
synchronization and communication on a shared-memory, shared-bus
multiprocessor system is described.  Adding an extra synchronization
bit to every word in shared memory, where this bit is cached together
with the word, and using all-read and all-write protocols of snoopy
cache achieve syn chronization and communication in an integrated
manner, not as separate mechanisms.  Since this mechanism assumes
single-assignment rule for memory words used for synchronization and
communication, and is expected to consume a large number of such
words, a mechanism for quickly reusing such words is also described.

      A synchronization bit is added to every word in shared memory
(Fig. 1).  This bit specifies that a data has been written to the
word already, and a program may now read it. This bit is 0 before a
data is written to the word and is 1 after it. All synchronization
bits are initialized to 0. For all memory words used for
synchronization and communication, the following functions are added
to the snoopy cache and shared memory.

      When writing to a word, the additional hardware to shared
memory sets the associated synchronization bit.  If a copy of the
word is in the cache, the additional hardware to cache sets the
associated synchronization bit in the cache.

      When reading from a word, a copy of the word (together with the
associated synchronization bit) is first included in the cache if it
is not already included.  Then the associated synchronization bit is
checked.  If it is 1, the cache returns the contents of the word to
the processor.  If it is 0, the cache puts the processor in a WAIT
state using the WAIT signal line. When a write to this word is
performed by another processor, the snoop mechanism of the cache (to
be described below) updates the word and the synchronization bit.
Thereafter the processor is restored from the WAIT state and reads
th...