Browse Prior Art Database

1 Nanosecond Lock Gating/1 Nanosecond Switch

IP.com Disclosure Number: IPCOM000101825D
Original Publication Date: 1990-Sep-01
Included in the Prior Art Database: 2005-Mar-16
Document File: 1 page(s) / 28K

Publishing Venue

IBM

Related People

Dixon, R: AUTHOR

Abstract

This article describes a fast circuit for use in an Intel 80386 microprocessor to gate the LOCK signal to an Intel 82385 cache controller.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 100% of the total text.

1 Nanosecond Lock Gating/1 Nanosecond Switch

       This article describes a fast circuit for use in an Intel
80386 microprocessor to gate the LOCK signal to an Intel 82385 cache
controller.

      Conventionally, transistor-to-transistor logic (TTL) is used to
gate the LOCK signal.  Operating System 2 (OS/2*) runs many locked
memory cycles.  At 20 MHz operation only 1 ns is allowed to gate the
LOCK signal.  This is not possible in TTL.  The circuit disclosed
herein provides this capability.

      The drawing is a diagram of the circuit of this disclosure.
Each locked memory cycle in a cache system is treated always as a
cache miss.  As locking is only required if one or more master
devices are installed, cycle locking is not needed in most
situations.  This circuit allows software (programmable option select
compatibility) gating of LOCK at 20 MHz operation, thereby improving
system performance.
* Trademark of IBM Corp.