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Direct Memory Access Translator for Using Personal Computer Devices Supporting Two DMA Protocols

IP.com Disclosure Number: IPCOM000101831D
Original Publication Date: 1990-Sep-01
Included in the Prior Art Database: 2005-Mar-16
Document File: 4 page(s) / 177K

Publishing Venue

IBM

Related People

Eng, RC: AUTHOR

Abstract

This article describes a method for translating direct memory access (DMA) requests of industrial and/or personal computer (PC) devices using discrete DMA request signals (type A device) to a PC system architecture which uses a bus arbitration DMA request protocol (type B system).

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 40% of the total text.

Direct Memory Access Translator for Using Personal Computer Devices Supporting Two DMA Protocols

       This article describes a method for translating direct
memory access (DMA) requests of industrial and/or personal computer
(PC) devices using discrete DMA request signals (type A device) to a
PC system architecture which uses a bus arbitration DMA request
protocol (type B system).

      PC adapter cards of type A create a request for a DMA cycle
when a movement of data between the adapter card and system memory is
required.  Requests for DMA are initiated by the adapter card
activating one of several DMA request lines of the PC bus.  A
computer system which supports the DMA protocol of both types A and B
device has these DMA request lines present on its bus, so that all
DMA requests from the type A adapter cards residing in the system are
routed to the DMA translator via the system bus.  The DMA translator
resides in an area of the system which contains common system
resources.

      The type A DMA requests are active high; in other words, an
active DMA request appears as a positive voltage on the DMA request
line of the system bus, while no request appears as a near zero
voltage level.  Because the DMA request line is transistor-transistor
logic (TTL) compatible, an unused DMA request line (a request line
which has no device attached) will "float" to a positive voltage
level (active DMA request).  Also, it is possible for several PC
adapters to share the same DMA request signal; one device owns and
drives the DMA request signal at a time, and the DMA request signal
is floated between ownership periods.  The "floating" (unconnected)
DMA request lines and the DMA request sharing present problems with
false DMA requests which are solved by this DMA translation method.

      The PC system of type B uses a different method for DMA
requests.  The DMA request lines are not present on the bus. The DMA
requests are initiated by the device arbitrating for control of the
bus on an arbitration level defined for the DMA device.  The DMA
cycle takes place when the device wins the arbitration and obtains
control of the bus.

      The DMA translation method described in this article basically
receives the PC type A DMA requests generated by the adapters
residing in the computer system, and translates the request to type B
protocol by arbitrating for control of the bus.  In addition, the DMA
translator handles the floating DMA request lines and suppresses the
false DMA requests.

      The DMA translation method is implemented as shown in the block
diagram in Fig. 1.  Fig. 2 is an expanded detail view of the request
mask register.  The DMA translator consists of a request mask for
each PC DMA type A request line, a priority encoder, a lookup table
with latched inputs, a bus arbiter, and a DMA translation sequencer.
Each PC DMA type A request signal of the bus is received by a request
mask.  A request mask consists...