Browse Prior Art Database

Stand-Alone Self-Test for Remote Chips

IP.com Disclosure Number: IPCOM000101834D
Original Publication Date: 1990-Sep-01
Included in the Prior Art Database: 2005-Mar-16
Document File: 4 page(s) / 106K

Publishing Venue

IBM

Related People

Badaoui, M: AUTHOR [+3]

Abstract

The general strategy to exercise chips before any operation is to use the self-test concept ST. This concept uses the LSSD structure of the chips fed by a Pseudo Random Pattern Generator (PRPG). The outputs of the various LSSD strings feed a Multiple Inputs Shift Register (MISR), in which signature is accumulated during the Self-Test operation.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 52% of the total text.

Stand-Alone Self-Test for Remote Chips

       The general strategy to exercise chips before any
operation is to use the self-test concept ST. This concept uses the
LSSD structure of the chips fed by a Pseudo Random Pattern Generator
(PRPG). The outputs of the various LSSD strings feed a Multiple
Inputs Shift Register (MISR), in which signature is accumulated
during the Self-Test operation.

      The different signals required to drive the chip(s) for ST
operation and signature gathering are provided by a dedicated logic,
common to all the chips that architecture allow to chain together.

      For remote chips not accessible from this Service Logic, there
is a problem to locally drive the Self-Test.

      For those components "self standing" remotely attached to upper
logical layers, the particle describes a solution which is to "auto
initiate and control" the Self-Test operation, run and exit of the
ST, keep signature in a register and turn over to the operational
mode.  Once the operational mode is activated, the signature can be
reported for analysis to upper layers.

      The proposed solution uses a portion of the functional cells of
the chips themselves to set up and drive the Self-Test mode of
operation. Signature will then be held in a register remotely
accessible in normal operation.

      The main features of the solution are as follows:
      - ST will be run at POR (Power-On Reset) time, or by a specific
command.
      - Run of ST will be disruptive for all chip interfaces.
      - PRPG has a width of 28 bits.
      - MISR will be 20 bits wide.
      - Maximum size of ST elementary strings limited according to
technology used.
      - Operational counter strings will be used for clock counting.
      - 2 x 64000 patterns will be run.

      Five successive phases have been determined for this approach,
each of them is detailed further:
      1- POR active (or detection of ST command).
      2- Flush reset of logic, PRPG and MISR.
      3- Preloading of MISR (if the feature is implemented).
      4- Run of ST sequences.
      5- Reset of logic.
      6- Operational mode.
      1- POR.

      This phase is defined as long as the POR line is active (low).
During this period, the...