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Charge Pump Circuit

IP.com Disclosure Number: IPCOM000101835D
Original Publication Date: 1990-Sep-01
Included in the Prior Art Database: 2005-Mar-16
Document File: 2 page(s) / 49K

Publishing Venue

IBM

Related People

Sakaue, Y: AUTHOR

Abstract

Disclosed is a CMOS circuit for efficient charge pumping under low VDD operation. The pumping efficiency is improved by eliminating the threshold voltage drop of MOS transistor switches.

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Charge Pump Circuit

       Disclosed is a CMOS circuit for efficient charge pumping
under low VDD operation. The pumping efficiency is improved by
eliminating the threshold voltage drop of MOS transistor switches.

      The disclosed charge pump circuit is shown in Fig. 1. The
threshold voltage (VTH) drop of MOS transistor switches is eliminated
by boosting the gate voltage. The transistor Q1 and the capacitor C1
boost the node 1 to the voltage above VDD. Q2 clamps the boosted
voltage to VDD + VTH, and helps Q5 to be turned off hard when CLK1
falls. Q3, Q4 and C2 control node 3. Q3 charges up the node 3 to
VDD - VTH when CLK3 is low, and C2 boosts the node 3 to 2VDD
- VTH as CLK3 rises. A higher boosted voltage is achieved with Q4
when the output voltage is higher than VDD. With these boosting
operations, the pump capacitor Cp is fully charged to VDD, boosted to
about 2VDD, and the charge is transferred to the output faster than
for conventional circuits.

      In order to obtain maximum efficiency, the charge pump circuit
is driven by two-phase non-overlapping clocks CLK1 and CLK3. Fig. 2.
shows the waveform of the clocks. The non-overlapping period does not
allow the charge to leak from the pump capacitor at each transition
of the clocks. When CLK2 falls, Q6 conducts and the charge leaks from
the output to Cp. CLK2 falls after CLK1 rises in order to charge Cp
mainly through Q5 and minimize the leakage. An implementation of the
clock generator is shown in Fi...