Browse Prior Art Database

Late Personalization of Function On VLSI Chips Without Using I/Os

IP.com Disclosure Number: IPCOM000101845D
Original Publication Date: 1990-Sep-01
Included in the Prior Art Database: 2005-Mar-17
Document File: 2 page(s) / 65K

Publishing Venue

IBM

Related People

Johnson, CL: AUTHOR [+2]

Abstract

This invention is an attractive alternative to current personalization techniques for VLSI chips. It does not use component I/Os. It does not require additional circuit development processes, and it preserves the potential of volume pricing for multi-function part. It is a trade-off between I/O usage and volume pricing, it draws the line as late as possible in the component manufacturing process to allow personalizations with minimum impact for volume pricing restrictions.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 64% of the total text.

Late Personalization of Function On VLSI Chips Without Using I/Os

       This invention is an attractive alternative to current
personalization techniques for VLSI chips.  It does not use component
I/Os.  It does not require additional circuit development processes,
and it preserves the potential of volume pricing for multi-function
part.  It is a trade-off between I/O usage and volume pricing, it
draws the line as late as possible in the component  manufacturing
process to allow personalizations with minimum impact for volume
pricing restrictions.

      Many of today's high-density VLSI chips have many more I/O
cells on the chip than can be supported by the package they are
mounted in.  It is the package (or component) I/O that is so
precious.  We simply design the functional decode in the normal
fashion (see the figure) using receivers in I/O cells with input
pull-ups or pull-downs as available.  The I/O cells which these
receivers occupy are not normally used as they do not connect to a
package I/O.  However, the C4 attached to the I/O cell is connected
to the GND or VDD bus on the package (GND connection if input
pull-ups are used, VDD connection if input pull- down is used).

      Ordinarily, all of the C4's are present on a chip. That being
the case, our decode reads all zero's (or all one's depending on
decode polarity).  If some of the C4's connecting to the decode
inputs are not present, that input will go to the opposite state,
thus we can...