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Generating Mains Disturbance Waveforms With a PS/2 or PC

IP.com Disclosure Number: IPCOM000101849D
Original Publication Date: 1990-Sep-01
Included in the Prior Art Database: 2005-Mar-17
Document File: 2 page(s) / 107K

Publishing Venue

IBM

Related People

Hayward, M: AUTHOR [+4]

Abstract

This article describes how a PS/2* or a PC can be used to generate uninterrupted variable waveforms from an adapter card with mounted DACs (digital-to-analog converters) by the manipulation of the timer control chip and interrupt handler. Advantages of flexibility and test-time savings result. A sample embodiment for generating PLDs (power line disturbances) is given in which timer interrupts are speeded up so that DACs can be driven directly in real time. Included is the generation of three-phase mains frequencies with disturbances purely under software control, allowing multiple test profiles to be easily compiled and saved.

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Generating Mains Disturbance Waveforms With a PS/2 or PC

       This article describes how a PS/2* or a PC can be used
to generate uninterrupted variable waveforms from an adapter card
with mounted DACs (digital-to-analog converters) by the manipulation
of the timer control chip and interrupt handler.  Advantages of
flexibility and test-time savings result.  A sample embodiment for
generating PLDs (power line disturbances) is given in which timer
interrupts are speeded up so that DACs can be driven directly in real
time. Included is the generation of three-phase mains frequencies
with disturbances purely under software control, allowing multiple
test profiles to be easily compiled and saved.

      In a standard IBM PC or PS/2 system, timer interrupts are
generated at 18.2 Hz.  The frequency of these interrupts is
determined by dividing the output of a 1.1925 MHz crystal oscillator.
This oscillator drives a timer chip which divides the oscillator by a
value determined by the contents of a 16-bit programmable register
within the timer chip, allowing division by any number between 1 and
65536.  In the standard configuration, the divide value is set to
65536 to give the 18.2 Hz interrupt rate.  To generate a higher
frequency interrupt requires reprogramming of the register. For
example, setting the divide value to 128 gives an interrupt frequency
of 9.316 kHz (512 times the original frequency).  Increasing the
timer tick frequency leads to problems if other steps are not taken,
e.g., existing system software assumes that the timer tick occurs at
18.2 Hz but as it is now running faster, various system functions
will malfunction.

      To resolve these problems, a new timer tick interrupt-handler
which is installed to perform the function to be done at the higher
frequency rate has to also perform some housekeeping.  The handler
has to keep track of how many interrupts have occurred and at every
512th (continuing the example) interrupt, it has to pass control to
the old timer tick routine.  In this way, the system software only
sees the original 18.2 Hz interrupt rate.  For those interrupts that
are not passed on to the old handler, the new handler also has to
reset the Intel 8259 hardware interrupt controller.  To keep the
housekeeping simple, the frequency multiplier should be restricted to
powers of 2.

      The length of time taken to process the interrupt must be kept
to a minimum.  If processing becomes too involved, the time taken to
service the timer interrupt will be longer than the interval between
interrupts.  To alleviate this, several approaches can be taken:  do
the absolute minimum of processing in the interrupt handler, optimize
an...