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Reference Voltage Generator for Dynamic Memories

IP.com Disclosure Number: IPCOM000101852D
Original Publication Date: 1990-Sep-01
Included in the Prior Art Database: 2005-Mar-17
Document File: 2 page(s) / 70K

Publishing Venue

IBM

Related People

Sakaue, Y: AUTHOR [+2]

Abstract

Disclosed is a CMOS circuit that reduces the bitline swing for the purpose of low power dynamic memory operation. Power dissipation for sensing is minimized by limiting the bitline voltage change to the wordline voltage change minus the threshold voltage of array devices.

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Reference Voltage Generator for Dynamic Memories

       Disclosed is a CMOS circuit that reduces the bitline
swing for the purpose of low power dynamic memory operation. Power
dissipation for sensing is minimized by limiting the bitline voltage
change to the wordline voltage change minus the threshold voltage of
array devices.

      A new method and CMOS circuit implementation are proposed for
the reduced bitline swing. Fig. 1 shows the concept of the new
method. The sense control circuit works in the period of signal
sensing, and the bitline voltage is changed from the precharged
voltage to a certain voltage. The voltage may be higher or lower than
the reference depending on each implementation of the sense control
circuit. Then, in the period of signal restoring, the bitline is
shorted to the reference voltage through the sense amplifier by
turning on the MOS switch A.

      The reference voltage generator has a source follower circuit
that subtracts the threshold voltage of a sample array device (VTH)
from the wordline voltage (VWL). The output (VWL - VTH) is buffered
to drive the VREF node that can be directly shorted to the huge load
of all bitlines selected during an access operation. The buffer
consists of a pair of differential amplifiers, the delta-V generator,
and the driver transistors.

      The differential amplifiers work as a comparator. They keep the
output voltage VREF identical to the source follower output voltage
(VWL - VTH) by changi...