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Browse Prior Art Database

Phase Noise Reduction Using Cascaded Variable Frequency Oscillators

IP.com Disclosure Number: IPCOM000101855D
Original Publication Date: 1990-Sep-01
Included in the Prior Art Database: 2005-Mar-17
Document File: 3 page(s) / 89K

Publishing Venue

IBM

Related People

Griess, KR: AUTHOR

Abstract

Disclosed is a method for phase noise reduction by cascading two or more Variable Frequency Oscillators (VFOs).

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 52% of the total text.

Phase Noise Reduction Using Cascaded Variable Frequency Oscillators

       Disclosed is a method for phase noise reduction by
cascading two or more Variable Frequency Oscillators (VFOs).

      Basically, the short term stability of a VFO is determined by
the frequency of update pulses to the phase detector, the natural
frequency (Wn) and the "smoothing" roll-off frequency Ws of the loop
filter.  It is also to some extent a function of the damping
coefficient D.

      For a VFO incorporating a second degree PLL (phase-locked loop)
the equations defining the loop performance are shown in Fig. 1
 where   Kv =   VCO gain
         Kd =   Phase Detector gain
         N  =   Integer value of the counter that divides
                FOUT
         Wn =   Loop Natural Frequency
         Ws =   "Smoothing" Roll-off Frequency
         D  =   Damping Coefficient
         R2 =   Loop Filter Resistor
      C1/C2 =   Loop Filter Capacitors

      The basic VFO (or frequency synthesizer) is shown in Fig. 2
 where   M  =   Integer value of the FREF divide-by counter
         N  =   Integer value of the FOUT divide-by counter
        PD  =   Phase-Frequency Detector
        LF  =   Active Loop Filter
       VCO  =   Voltage Controlled Oscillator

      In general, to minimize jitter, Wn should be made as small as
possible without violating any lock-up time criteria.  Ws, which
helps to reduce the modulation effects of the reference clock, should
be placed well below FREF/M and also well above Wn (to prevent
instability).  D should be set somewhere around .7 to 1.0.  Also, M
and N should be kept small to maximize the number of update pulses to
the phase detector per unit time.

      This represents a lot of criteria to be met and is quite
difficult, if not impossible to do, and still keep physical values
realizable for the loop filter components. This is especially true if
FREF is much smaller than FOUT. Having FREF << FOUT genera...